From dca39c26f95b3a58135a68ec274e558afcb43180 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 22 Jan 2016 15:45:16 +0200 Subject: [PATCH] ad6676evb: Added clock constraint for the ADC path --- projects/ad6676evb/vc707/system_constr.xdc | 1 + projects/ad6676evb/zc706/system_constr.xdc | 1 + 2 files changed, 2 insertions(+) diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc index f94a3e050..a7ad92199 100644 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -31,3 +31,4 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] # clocks create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc index d43eb93b0..44e3a8ee7 100644 --- a/projects/ad6676evb/zc706/system_constr.xdc +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -31,3 +31,4 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4 # clocks create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]