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ad6676evb: Added clock constraint for the ADC path

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Adrian Costina 2016-01-22 15:45:16 +02:00
parent 9cd0378003
commit dca39c26f9
2 changed files with 2 additions and 0 deletions
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1
projects/ad6676evb/vc707/system_constr.xdc
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@ -31,3 +31,4 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
# clocks # clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

1
projects/ad6676evb/zc706/system_constr.xdc
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@ -31,3 +31,4 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4
# clocks # clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]