diff --git a/projects/ad7768evb/common/ad7768_if.v b/projects/ad7768evb/common/ad7768_if.v
index e9296a35f..bd85836c5 100644
--- a/projects/ad7768evb/common/ad7768_if.v
+++ b/projects/ad7768evb/common/ad7768_if.v
@@ -48,6 +48,7 @@ module ad7768_if (
   output                  adc_clk,
   output  reg             adc_valid,
   output  reg [ 31:0]     adc_data,
+  output                  adc_sync,
 
   // control interface
 
@@ -136,6 +137,7 @@ module ad7768_if (
   reg     [ 35:0]   adc_status_clr_m1 = 'd0;
   reg     [ 35:0]   adc_status_clr = 'd0;
   reg     [ 35:0]   adc_status_clr_d = 'd0;
+  reg               adc_valid_d = 'd0;
 
   // internal signals
 
@@ -245,6 +247,11 @@ module ad7768_if (
 
   // data & status
 
+  always @(posedge adc_clk) begin
+    adc_valid_d <= adc_valid;
+  end
+  assign adc_sync = adc_valid & ~adc_valid_d;
+
   always @(posedge adc_clk) begin
     adc_valid <= adc_valid_int & adc_enable_int;
     adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]};
diff --git a/projects/ad7768evb/common/ad7768evb_bd.tcl b/projects/ad7768evb/common/ad7768evb_bd.tcl
index d69e321f5..ad06410e9 100644
--- a/projects/ad7768evb/common/ad7768evb_bd.tcl
+++ b/projects/ad7768evb/common/ad7768evb_bd.tcl
@@ -3,6 +3,7 @@
 
 create_bd_port -dir I adc_clk
 create_bd_port -dir I adc_valid
+create_bd_port -dir I adc_sync
 create_bd_port -dir I -from 31 -to 0 adc_data
 create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
 create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
@@ -39,6 +40,7 @@ ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1
 
 ad_connect  adc_clk ad7768_dma/fifo_wr_clk
 ad_connect  adc_valid ad7768_dma/fifo_wr_en
+ad_connect  adc_sync ad7768_dma/fifo_wr_sync
 ad_connect  adc_data ad7768_dma/fifo_wr_din
 ad_connect  adc_gpio_0_i ad7768_gpio/gpio_io_i
 ad_connect  adc_gpio_0_o ad7768_gpio/gpio_io_o
diff --git a/projects/ad7768evb/zed/system_top.v b/projects/ad7768evb/zed/system_top.v
index 1299ae29a..b9690379f 100644
--- a/projects/ad7768evb/zed/system_top.v
+++ b/projects/ad7768evb/zed/system_top.v
@@ -107,6 +107,7 @@ module system_top (
 
   wire            adc_clk;
   wire            adc_valid;
+  wire            adc_sync;
   wire    [31:0]  adc_data;
   wire            up_sshot;
   wire    [ 1:0]  up_format;
@@ -178,6 +179,7 @@ module system_top (
     .data_in (data_in),
     .adc_clk (adc_clk),
     .adc_valid (adc_valid),
+    .adc_sync (adc_sync),
     .adc_data (adc_data),
     .up_sshot (up_sshot),
     .up_format (up_format),
@@ -196,6 +198,7 @@ module system_top (
     .adc_gpio_1_o (adc_gpio_o[63:32]),
     .adc_gpio_1_t (adc_gpio_t[63:32]),
     .adc_valid (adc_valid),
+    .adc_sync (adc_sync),
     .ddr_addr (ddr_addr),
     .ddr_ba (ddr_ba),
     .ddr_cas_n (ddr_cas_n),