diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl
index 0812c16a7..68df73ba4 100644
--- a/projects/adrv9001/common/adrv9001_bd.tcl
+++ b/projects/adrv9001/common/adrv9001_bd.tcl
@@ -1,3 +1,9 @@
+# create debug ports
+create_bd_port -dir O adc1_div_clk
+create_bd_port -dir O adc2_div_clk
+create_bd_port -dir O dac1_div_clk
+create_bd_port -dir O dac2_div_clk
+
 create_bd_port -dir I ref_clk
 
 create_bd_port -dir I tx_output_enable
@@ -286,3 +292,10 @@ ad_cpu_interrupt ps-12 mb-11 axi_adrv9001_rx2_dma/irq
 ad_cpu_interrupt ps-11 mb-6 axi_adrv9001_tx1_dma/irq
 ad_cpu_interrupt ps-10 mb-5 axi_adrv9001_tx2_dma/irq
 
+
+# Connect debug ports
+ad_connect  axi_adrv9001/adc_1_clk adc1_div_clk
+ad_connect  axi_adrv9001/adc_2_clk adc2_div_clk
+ad_connect  axi_adrv9001/dac_1_clk dac1_div_clk
+ad_connect  axi_adrv9001/dac_2_clk dac2_div_clk
+
diff --git a/projects/adrv9001/zcu102/system_constr.xdc b/projects/adrv9001/zcu102/system_constr.xdc
index af18449fd..9f6458de2 100644
--- a/projects/adrv9001/zcu102/system_constr.xdc
+++ b/projects/adrv9001/zcu102/system_constr.xdc
@@ -44,3 +44,15 @@ set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_out_p]
 
 set_property  -dict {PACKAGE_PIN A20   IOSTANDARD LVCMOS33} [get_ports tdd_sync]   ;#PMOD0_0 J55.1
 
+# Debug port (Proto header)
+set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports proto_hdr[0]]  ;# J3 24 L8P_HDGC_50_P
+set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports proto_hdr[1]]  ;# J3 22 L8N_HDGC_50_N
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports proto_hdr[2]]  ;# J3 20 L11P_AD9P_50_P
+set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports proto_hdr[3]]  ;# J3 18 L11N_AD9N_50_N
+set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports proto_hdr[4]]  ;# J3 16 L12P_AD8P_50_P
+set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports proto_hdr[5]]  ;# J3 14 L12N_AD8N_50_N
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports proto_hdr[6]]  ;# J3 12 L9P_AD11P_50_P
+set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports proto_hdr[7]]  ;# J3 10 L9N_AD11N_50_N
+set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports proto_hdr[8]]  ;# J3  8 L10P_AD10P_50_P
+set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports proto_hdr[9]]  ;# J3  6 L10N_AD10N_50_N
+
diff --git a/projects/adrv9001/zcu102/system_top.v b/projects/adrv9001/zcu102/system_top.v
index 94716a2c7..7b2611992 100644
--- a/projects/adrv9001/zcu102/system_top.v
+++ b/projects/adrv9001/zcu102/system_top.v
@@ -124,7 +124,11 @@ module system_top (
   input                   vadj_err,
   output                  platform_status,
 
-  inout                   tdd_sync
+  inout                   tdd_sync,
+
+  //debug hdr
+  output       [9:0]      proto_hdr
+
 );
   // internal registers
   reg         [  2:0] mcs_sync_m = 'd0;
@@ -290,8 +294,18 @@ module system_top (
     .spi1_sclk (),
     .spi1_csn (),
     .spi1_miso (1'b0),
-    .spi1_mosi ()
+    .spi1_mosi (),
+
+    // debug
+    .adc1_div_clk (proto_hdr[0]),
+    .adc2_div_clk (proto_hdr[1]),
+    .dac1_div_clk (proto_hdr[2]),
+    .dac2_div_clk (proto_hdr[3])
+
   );
+
+  assign proto_hdr[9:4] = {'b0};
+
 endmodule
 
 // ***************************************************************************