From dd6983647303771e63dc55d3546da63d2d7f636d Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 3 Apr 2018 10:13:05 +0300 Subject: [PATCH] util_dacfifo: Infer clock and reset signals --- library/util_dacfifo/util_dacfifo_ip.tcl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/library/util_dacfifo/util_dacfifo_ip.tcl b/library/util_dacfifo/util_dacfifo_ip.tcl index 593f4f162..29ebe59f9 100644 --- a/library/util_dacfifo/util_dacfifo_ip.tcl +++ b/library/util_dacfifo/util_dacfifo_ip.tcl @@ -13,6 +13,10 @@ adi_ip_files util_dacfifo [list \ adi_ip_properties_lite util_dacfifo -ipx::remove_all_bus_interface [ipx::current_core] +ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::save_core [ipx::current_core]