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util_dacfifo: Infer clock and reset signals

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Adrian Costina 2018-04-03 10:13:05 +03:00 committed by István Csomortáni
parent 3436210429
commit dd69836473
1 changed files with 5 additions and 1 deletions
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6
library/util_dacfifo/util_dacfifo_ip.tcl
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@ -13,6 +13,10 @@ adi_ip_files util_dacfifo [list \
adi_ip_properties_lite util_dacfifo
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]