axi_dmac: bundle AXI Stream signals into bus for Intel
Add signals that are optional by standard but required by the axi4stream interface definition. Make them selectable by parameters.main
Laszlo Nagy
Laszlo Nagy
parent
7f16f823ff
commit
dd952ddad1
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@ -58,6 +58,8 @@ module axi_dmac #(
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parameter FIFO_SIZE = 8, // In bursts
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parameter AXI_ID_WIDTH_SRC = 1,
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parameter AXI_ID_WIDTH_DEST = 1,
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parameter DMA_AXIS_ID_W = 8,
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parameter DMA_AXIS_DEST_W = 4,
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter ENABLE_DIAGNOSTICS_IF = 0,
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parameter ALLOW_ASYM_MEM = 0
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@ -190,7 +192,11 @@ module axi_dmac #(
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output s_axis_ready,
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input s_axis_valid,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [DMA_DATA_WIDTH_SRC/8-1:0] s_axis_strb,
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input [DMA_DATA_WIDTH_SRC/8-1:0] s_axis_keep,
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input [0:0] s_axis_user,
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input [DMA_AXIS_ID_W-1:0] s_axis_id,
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input [DMA_AXIS_DEST_W-1:0] s_axis_dest,
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input s_axis_last,
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output s_axis_xfer_req,
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@ -199,6 +205,11 @@ module axi_dmac #(
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input m_axis_ready,
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output m_axis_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output [DMA_DATA_WIDTH_DEST/8-1:0] m_axis_strb,
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output [DMA_DATA_WIDTH_DEST/8-1:0] m_axis_keep,
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output [0:0] m_axis_user,
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output [DMA_AXIS_ID_W-1:0] m_axis_id,
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output [DMA_AXIS_DEST_W-1:0] m_axis_dest,
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output m_axis_last,
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output m_axis_xfer_req,
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@ -606,4 +617,10 @@ assign m_src_axi_wdata = 'h0;
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assign m_src_axi_wstrb = 'h0;
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assign m_src_axi_wlast = 'h0;
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assign m_axis_keep = {DMA_DATA_WIDTH_DEST/8{1'b1}};
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assign m_axis_strb = {DMA_DATA_WIDTH_DEST/8{1'b1}};
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assign m_axis_id = 'h0;
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assign m_axis_dest = 'h0;
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assign m_axis_user = 'h0;
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endmodule
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@ -290,18 +290,36 @@ add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1
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# axis destination/source
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ad_alt_intf clock m_axis_aclk input 1 clk
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ad_alt_intf signal m_axis_valid output 1 valid
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ad_alt_intf signal m_axis_data output DMA_DATA_WIDTH_DEST data
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ad_alt_intf signal m_axis_ready input 1 ready
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ad_alt_intf signal m_axis_last output 1 last
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ad_alt_intf signal m_axis_xfer_req output 1 xfer_req
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add_interface m_axis axi4stream start
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set_interface_property m_axis associatedClock if_m_axis_aclk
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set_interface_property m_axis associatedReset s_axi_reset
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add_interface_port m_axis m_axis_valid tvalid Output 1
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add_interface_port m_axis m_axis_last tlast Output 1
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add_interface_port m_axis m_axis_ready tready Input 1
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add_interface_port m_axis m_axis_data tdata Output DMA_DATA_WIDTH_DEST
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add_interface_port m_axis m_axis_user tuser Output 1
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add_interface_port m_axis m_axis_id tid Output DMA_AXIS_ID_W
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add_interface_port m_axis m_axis_dest tdest Output DMA_AXIS_DEST_W
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add_interface_port m_axis m_axis_strb tstrb Output DMA_DATA_WIDTH_DEST/8
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add_interface_port m_axis m_axis_keep tkeep Output DMA_DATA_WIDTH_DEST/8
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ad_alt_intf clock s_axis_aclk input 1 clk
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ad_alt_intf signal s_axis_valid input 1 valid
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ad_alt_intf signal s_axis_data input DMA_DATA_WIDTH_SRC data
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ad_alt_intf signal s_axis_ready output 1 ready
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ad_alt_intf signal s_axis_xfer_req output 1 xfer_req
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ad_alt_intf signal s_axis_user input 1 user
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add_interface s_axis axi4stream end
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set_interface_property s_axis associatedClock if_s_axis_aclk
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set_interface_property s_axis associatedReset s_axi_reset
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add_interface_port s_axis s_axis_valid tvalid Input 1
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add_interface_port s_axis s_axis_last tlast Input 1
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add_interface_port s_axis s_axis_ready tready Output 1
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add_interface_port s_axis s_axis_data tdata Input DMA_DATA_WIDTH_SRC
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add_interface_port s_axis s_axis_user tuser Input 1
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add_interface_port s_axis s_axis_id tid Input DMA_AXIS_ID_W
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add_interface_port s_axis s_axis_dest tdest Input DMA_AXIS_DEST_W
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add_interface_port s_axis s_axis_strb tstrb Input DMA_DATA_WIDTH_SRC/8
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add_interface_port s_axis s_axis_keep tkeep Input DMA_DATA_WIDTH_SRC/8
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# fifo destination/source
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@ -409,21 +427,57 @@ proc axi_dmac_elaborate {} {
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# axis destination/source
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if {[get_parameter_value DMA_TYPE_DEST] != 1} {
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lappend disabled_intfs \
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if_m_axis_aclk if_m_axis_valid if_m_axis_data if_m_axis_ready \
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if_m_axis_last if_m_axis_xfer_req
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lappend disabled_intfs if_m_axis_aclk if_m_axis_xfer_req m_axis
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} else {
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if {[get_parameter_value HAS_AXIS_TSTRB] == 0} {
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set_port_property m_axis_strb termination true
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}
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if {[get_parameter_value HAS_AXIS_TKEEP] == 0} {
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set_port_property m_axis_keep termination true
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}
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if {[get_parameter_value HAS_AXIS_TLAST] == 0} {
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set_port_property m_axis_last termination true
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}
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if {[get_parameter_value HAS_AXIS_TID] == 0} {
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set_port_property m_axis_id termination true
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}
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if {[get_parameter_value HAS_AXIS_TDEST] == 0} {
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set_port_property m_axis_dest termination true
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}
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if {[get_parameter_value HAS_AXIS_TUSER] == 0} {
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set_port_property m_axis_user termination true
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}
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}
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if {[get_parameter_value DMA_TYPE_SRC] != 1} {
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lappend disabled_intfs \
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if_s_axis_aclk if_s_axis_valid if_s_axis_data if_s_axis_ready \
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if_s_axis_xfer_req if_s_axis_user
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}
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if {[get_parameter_value DMA_TYPE_SRC] == 1 &&
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[get_parameter_value SYNC_TRANSFER_START] == 0} {
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set_port_property s_axis_user termination true
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set_port_property s_axis_user termination_value 1
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lappend disabled_intfs if_s_axis_aclk if_s_axis_xfer_req s_axis
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} else {
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if {[get_parameter_value HAS_AXIS_TSTRB] == 0} {
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set_port_property s_axis_strb termination true
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set_port_property s_axis_strb termination_value 0xFF
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}
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if {[get_parameter_value HAS_AXIS_TKEEP] == 0} {
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set_port_property s_axis_keep termination true
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set_port_property s_axis_keep termination_value 0xFF
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}
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if {[get_parameter_value HAS_AXIS_TLAST] == 0} {
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set_port_property s_axis_last termination true
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set_port_property s_axis_last termination_value 0
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}
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if {[get_parameter_value HAS_AXIS_TID] == 0} {
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set_port_property s_axis_id termination true
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set_port_property s_axis_id termination_value 0
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}
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if {[get_parameter_value HAS_AXIS_TDEST] == 0} {
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set_port_property s_axis_dest termination true
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set_port_property s_axis_dest termination_value 0
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}
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if {[get_parameter_value HAS_AXIS_TUSER] == 0} {
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if {[get_parameter_value SYNC_TRANSFER_START] == 0} {
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set_port_property s_axis_user termination true
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set_port_property s_axis_user termination_value 0
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}
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}
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}
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# fifo destination/source
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@ -471,3 +525,51 @@ set_parameter_property ENABLE_DIAGNOSTICS_IF GROUP $group
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add_interface diagnostics_if conduit end
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add_interface_port diagnostics_if dest_diag_level_bursts dest_diag_level_bursts Output "8"
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set group "AXI Stream interface common configuration"
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add_parameter HAS_AXIS_TSTRB INTEGER 0
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set_parameter_property HAS_AXIS_TSTRB DISPLAY_NAME "AXI Stream interface has TSTRB"
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set_parameter_property HAS_AXIS_TSTRB DISPLAY_HINT boolean
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set_parameter_property HAS_AXIS_TSTRB HDL_PARAMETER false
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set_parameter_property HAS_AXIS_TSTRB GROUP $group
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add_parameter HAS_AXIS_TKEEP INTEGER 0
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set_parameter_property HAS_AXIS_TKEEP DISPLAY_NAME "AXI Stream interface has TKEEP"
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set_parameter_property HAS_AXIS_TKEEP DISPLAY_HINT boolean
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set_parameter_property HAS_AXIS_TKEEP HDL_PARAMETER false
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set_parameter_property HAS_AXIS_TKEEP GROUP $group
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add_parameter HAS_AXIS_TLAST INTEGER 0
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set_parameter_property HAS_AXIS_TLAST DISPLAY_NAME "AXI Stream interface has TLAST"
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set_parameter_property HAS_AXIS_TLAST DISPLAY_HINT boolean
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set_parameter_property HAS_AXIS_TLAST HDL_PARAMETER false
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set_parameter_property HAS_AXIS_TLAST GROUP $group
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add_parameter HAS_AXIS_TID INTEGER 0
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set_parameter_property HAS_AXIS_TID DISPLAY_NAME "AXI Stream interface has TID"
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set_parameter_property HAS_AXIS_TID DISPLAY_HINT boolean
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set_parameter_property HAS_AXIS_TID HDL_PARAMETER false
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set_parameter_property HAS_AXIS_TID GROUP $group
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add_parameter DMA_AXIS_ID_W INTEGER 8
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set_parameter_property DMA_AXIS_ID_W DISPLAY_NAME "AXI Stream TID width"
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set_parameter_property DMA_AXIS_ID_W HDL_PARAMETER true
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set_parameter_property DMA_AXIS_ID_W GROUP $group
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add_parameter HAS_AXIS_TDEST INTEGER 0
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set_parameter_property HAS_AXIS_TDEST DISPLAY_NAME "AXI Stream interface has TDEST"
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set_parameter_property HAS_AXIS_TDEST DISPLAY_HINT boolean
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set_parameter_property HAS_AXIS_TDEST HDL_PARAMETER false
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set_parameter_property HAS_AXIS_TDEST GROUP $group
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add_parameter DMA_AXIS_DEST_W INTEGER 4
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set_parameter_property DMA_AXIS_DEST_W DISPLAY_NAME "AXI Stream TDEST width"
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set_parameter_property DMA_AXIS_DEST_W HDL_PARAMETER true
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set_parameter_property DMA_AXIS_DEST_W GROUP $group
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add_parameter HAS_AXIS_TUSER INTEGER 0
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set_parameter_property HAS_AXIS_TUSER DISPLAY_NAME "AXI Stream interface has TUSER"
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set_parameter_property HAS_AXIS_TUSER DISPLAY_HINT boolean
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set_parameter_property HAS_AXIS_TUSER HDL_PARAMETER false
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set_parameter_property HAS_AXIS_TUSER GROUP $group
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@ -395,6 +395,8 @@ ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc]
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ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc]
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ipx::create_xgui_files [ipx::current_core]
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ipx::save_core $cc
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