fmcomms2/a10soc: compile version
Rejeesh Kutty
parent
f4e5965936
commit
ddfaff2cf5
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@ -315,6 +315,11 @@
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internal="fmcomms2.axi_ad9361_device_if"
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type="conduit"
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dir="end" />
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<interface
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name="delay_clk"
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internal="fmcomms2.axi_ad9361_delay_clk"
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type="clock"
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dir="end" />
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<interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
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<interface
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name="hps_ddr_oct"
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@ -346,27 +351,37 @@
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internal="sys_clk.clk_in_reset"
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type="reset"
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dir="end" />
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<interface
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name="up_enable"
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internal="fmcomms2.axi_ad9361_up_enable"
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type="conduit"
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dir="end" />
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<interface
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name="up_txnrx"
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internal="fmcomms2.axi_ad9361_up_txnrx"
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type="conduit"
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dir="end" />
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<module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
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<parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="4" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="4" />
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<parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
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<parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
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<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
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<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
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<parameter name="AUTO_UNIQUE_ID" value="system_bd_a10soc" />
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<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
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</module>
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<module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
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<parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_RATE" value="0" />
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<parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
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<parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
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<parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
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<parameter
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name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
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@ -379,10 +394,10 @@
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<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
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<parameter name="AUTO_UNIQUE_ID" value="system_bd_fmcomms2" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
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<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
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</module>
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<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
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<parameter name="clockFrequency" value="100000000" />
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@ -435,11 +450,6 @@
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<parameter name="baseAddress" value="0x00010000" />
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<parameter name="defaultConnection" value="false" />
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</connection>
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<connection
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kind="clock"
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version="15.1"
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start="fmcomms2.axi_ad9361_l_clk"
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end="fmcomms2.axi_ad9361_device_clock" />
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<connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
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<connection
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kind="clock"
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@ -1,43 +1,7 @@
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}]
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create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}]
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create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk_in}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
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i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
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i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]
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set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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@ -11,5 +11,120 @@ set_global_assignment -name VERILOG_FILE system_top.v
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set_global_assignment -name SDC_FILE system_constr.sdc
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set_global_assignment -name TOP_LEVEL_ENTITY system_top
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# data-path
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set_location_assignment PIN_G14 -to rx_clk_in ; ## G6 FMC_LPC_LA00_CC_P
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set_location_assignment PIN_H14 -to "rx_clk_in(n)" ; ## G7 FMC_LPC_LA00_CC_N
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set_location_assignment PIN_E12 -to rx_frame_in ; ## D8 FMC_LPC_LA01_CC_P
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set_location_assignment PIN_E13 -to "rx_frame_in(n)" ; ## D9 FMC_LPC_LA01_CC_N
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set_location_assignment PIN_C13 -to rx_data_in[0] ; ## H7 FMC_LPC_LA02_P
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set_location_assignment PIN_D13 -to "rx_data_in[0](n)" ; ## H8 FMC_LPC_LA02_N
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set_location_assignment PIN_C14 -to rx_data_in[1] ; ## G9 FMC_LPC_LA03_P
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set_location_assignment PIN_D14 -to "rx_data_in[1](n)" ; ## G10 FMC_LPC_LA03_N
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set_location_assignment PIN_H12 -to rx_data_in[2] ; ## H10 FMC_LPC_LA04_P
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set_location_assignment PIN_H13 -to "rx_data_in[2](n)" ; ## H11 FMC_LPC_LA04_N
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set_location_assignment PIN_F13 -to rx_data_in[3] ; ## D11 FMC_LPC_LA05_P
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set_location_assignment PIN_F14 -to "rx_data_in[3](n)" ; ## D12 FMC_LPC_LA05_N
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set_location_assignment PIN_A10 -to rx_data_in[4] ; ## C10 FMC_LPC_LA06_P
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set_location_assignment PIN_B10 -to "rx_data_in[4](n)" ; ## C11 FMC_LPC_LA06_N
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set_location_assignment PIN_A9 -to rx_data_in[5] ; ## H13 FMC_LPC_LA07_P
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set_location_assignment PIN_B9 -to "rx_data_in[5](n)" ; ## H14 FMC_LPC_LA07_N
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set_location_assignment PIN_B11 -to tx_clk_out ; ## G12 FMC_LPC_LA08_P
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set_location_assignment PIN_B12 -to "tx_clk_out(n)" ; ## G13 FMC_LPC_LA08_N
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set_location_assignment PIN_A12 -to tx_frame_out ; ## D14 FMC_LPC_LA09_P
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set_location_assignment PIN_A13 -to "tx_frame_out(n)" ; ## D15 FMC_LPC_LA09_N
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set_location_assignment PIN_C9 -to tx_data_out[0] ; ## H16 FMC_LPC_LA11_P
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set_location_assignment PIN_D9 -to "tx_data_out[0](n)" ; ## H17 FMC_LPC_LA11_N
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set_location_assignment PIN_M12 -to tx_data_out[1] ; ## G15 FMC_LPC_LA12_P
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set_location_assignment PIN_N13 -to "tx_data_out[1](n)" ; ## G16 FMC_LPC_LA12_N
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set_location_assignment PIN_J11 -to tx_data_out[2] ; ## D17 FMC_LPC_LA13_P
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set_location_assignment PIN_K11 -to "tx_data_out[2](n)" ; ## D18 FMC_LPC_LA13_N
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set_location_assignment PIN_A7 -to tx_data_out[3] ; ## C14 FMC_LPC_LA10_P
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set_location_assignment PIN_A8 -to "tx_data_out[3](n)" ; ## C15 FMC_LPC_LA10_N
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set_location_assignment PIN_J9 -to tx_data_out[4] ; ## C18 FMC_LPC_LA14_P
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set_location_assignment PIN_J10 -to "tx_data_out[4](n)" ; ## C19 FMC_LPC_LA14_N
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set_location_assignment PIN_D4 -to tx_data_out[5] ; ## H19 FMC_LPC_LA15_P
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set_location_assignment PIN_D5 -to "tx_data_out[5](n)" ; ## H20 FMC_LPC_LA15_N
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set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
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set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out
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set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_clk_in
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_frame_in
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[0]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[1]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[2]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
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# ensm/tdd control
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set_location_assignment PIN_D6 -to enable ; ## G18 FMC_LPC_LA16_P
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set_location_assignment PIN_E6 -to txnrx ; ## G19 FMC_LPC_LA16_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to enable
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set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx
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# control & status
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set_location_assignment PIN_C3 -to gpio_status[0] ; ## G21 FMC_LPC_LA20_P
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set_location_assignment PIN_C4 -to gpio_status[1] ; ## G22 FMC_LPC_LA20_N
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set_location_assignment PIN_C2 -to gpio_status[2] ; ## H25 FMC_LPC_LA21_P
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set_location_assignment PIN_D3 -to gpio_status[3] ; ## H26 FMC_LPC_LA21_N
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set_location_assignment PIN_F4 -to gpio_status[4] ; ## G24 FMC_LPC_LA22_P
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set_location_assignment PIN_G4 -to gpio_status[5] ; ## G25 FMC_LPC_LA22_N
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set_location_assignment PIN_C1 -to gpio_status[6] ; ## D23 FMC_LPC_LA23_P
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set_location_assignment PIN_D1 -to gpio_status[7] ; ## D24 FMC_LPC_LA23_N
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set_location_assignment PIN_E1 -to gpio_ctl[0] ; ## H28 FMC_LPC_LA24_P
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set_location_assignment PIN_E2 -to gpio_ctl[1] ; ## H29 FMC_LPC_LA24_N
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set_location_assignment PIN_E3 -to gpio_ctl[2] ; ## G27 FMC_LPC_LA25_P
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set_location_assignment PIN_F3 -to gpio_ctl[3] ; ## G28 FMC_LPC_LA25_N
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set_location_assignment PIN_G5 -to gpio_en_agc ; ## H22 FMC_LPC_LA19_P
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set_location_assignment PIN_G6 -to gpio_sync ; ## H23 FMC_LPC_LA19_N
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set_location_assignment PIN_L5 -to gpio_resetb ; ## H31 FMC_LPC_LA28_P
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb
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# spi
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set_location_assignment PIN_F2 -to spi_csn ; ## D26 FMC_LPC_LA26_P
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set_location_assignment PIN_G2 -to spi_clk ; ## D27 FMC_LPC_LA26_N
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set_location_assignment PIN_G1 -to spi_mosi ; ## C26 FMC_LPC_LA27_P
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set_location_assignment PIN_H2 -to spi_miso ; ## C27 FMC_LPC_LA27_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
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set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
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execute_flow -compile
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@ -41,246 +41,222 @@ module system_top (
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// clock and resets
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sys_clk,
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sys_resetn,
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input sys_clk,
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input sys_resetn,
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// ddr3
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// hps-ddr4 (32)
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ddr3_clk_p,
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ddr3_clk_n,
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ddr3_a,
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ddr3_ba,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_odt,
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ddr3_reset_n,
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ddr3_we_n,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_dq,
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ddr3_dm,
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ddr3_rzq,
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ddr3_ref_clk,
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input hps_ddr_ref_clk,
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||||
output [ 0:0] hps_ddr_clk_p,
|
||||
output [ 0:0] hps_ddr_clk_n,
|
||||
output [ 16:0] hsp_ddr_a,
|
||||
output [ 1:0] hps_ddr_ba,
|
||||
output [ 0:0] hps_ddr_bg,
|
||||
output [ 0:0] hps_ddr_cke,
|
||||
output [ 0:0] hps_ddr_cs_n,
|
||||
output [ 0:0] hps_ddr_odt,
|
||||
output [ 0:0] hps_ddr_reset_n,
|
||||
output [ 0:0] hps_ddr_act_n,
|
||||
output [ 0:0] hps_ddr_par,
|
||||
input [ 0:0] hps_ddr_alert_n,
|
||||
inout [ 3:0] hps_ddr_dqs_p,
|
||||
inout [ 3:0] hps_ddr_dqs_n,
|
||||
inout [ 31:0] hps_ddr_dq,
|
||||
inout [ 3:0] hps_ddr_dbi_n,
|
||||
input hps_ddr_rzq,
|
||||
|
||||
// ethernet
|
||||
// hps-ethernet
|
||||
|
||||
eth_ref_clk,
|
||||
eth_rxd,
|
||||
eth_txd,
|
||||
eth_mdc,
|
||||
eth_mdio,
|
||||
eth_resetn,
|
||||
eth_intn,
|
||||
input [ 0:0] hps_eth_rxclk,
|
||||
input [ 0:0] hps_eth_rxctl,
|
||||
input [ 3:0] hps_eth_rxd,
|
||||
output [ 0:0] hps_eth_txclk,
|
||||
output [ 0:0] hps_eth_txctl,
|
||||
output [ 3:0] hps_eth_txd,
|
||||
output [ 0:0] hps_eth_mdc,
|
||||
inout [ 0:0] hps_eth_mdio,
|
||||
|
||||
// board gpio
|
||||
// hps-sdio
|
||||
|
||||
gpio_bd_i,
|
||||
gpio_bd_o,
|
||||
output [ 0:0] hps_sdio_clk,
|
||||
inout [ 0:0] hps_sdio_cmd,
|
||||
inout [ 7:0] hps_sdio_d,
|
||||
|
||||
// lane interface
|
||||
// hps-usb
|
||||
|
||||
rx_ref_clk,
|
||||
rx_sysref,
|
||||
rx_sync,
|
||||
rx_data,
|
||||
tx_ref_clk,
|
||||
tx_sysref,
|
||||
tx_sync,
|
||||
tx_data,
|
||||
input [ 0:0] hps_usb_clk,
|
||||
input [ 0:0] hps_usb_dir,
|
||||
input [ 0:0] hps_usb_nxt,
|
||||
output [ 0:0] hps_usb_stp,
|
||||
inout [ 7:0] hps_usb_d,
|
||||
|
||||
// gpio
|
||||
// hps-uart
|
||||
|
||||
trig,
|
||||
adc_fdb,
|
||||
adc_fda,
|
||||
dac_irq,
|
||||
clkd_status,
|
||||
adc_pd,
|
||||
dac_txen,
|
||||
dac_reset,
|
||||
clkd_sync,
|
||||
input [ 0:0] hps_uart_rx,
|
||||
output [ 0:0] hps_uart_tx,
|
||||
|
||||
// spi
|
||||
// hps-i2c (shared w fmc-a, fmc-b)
|
||||
|
||||
spi_csn_clk,
|
||||
spi_csn_dac,
|
||||
spi_csn_adc,
|
||||
spi_clk,
|
||||
spi_sdio,
|
||||
spi_dir);
|
||||
inout [ 0:0] hps_i2c_sda,
|
||||
inout [ 0:0] hps_i2c_scl,
|
||||
|
||||
// clock and resets
|
||||
// hps-gpio (max-v-u16)
|
||||
|
||||
input sys_clk;
|
||||
input sys_resetn;
|
||||
inout [ 3:0] hps_gpio,
|
||||
|
||||
// gpio (max-v-u21)
|
||||
|
||||
// ddr3
|
||||
input [ 7:0] gpio_bd_i,
|
||||
output [ 3:0] gpio_bd_o,
|
||||
|
||||
output ddr3_clk_p;
|
||||
output ddr3_clk_n;
|
||||
output [ 14:0] ddr3_a;
|
||||
output [ 2:0] ddr3_ba;
|
||||
output ddr3_cke;
|
||||
output ddr3_cs_n;
|
||||
output ddr3_odt;
|
||||
output ddr3_reset_n;
|
||||
output ddr3_we_n;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_cas_n;
|
||||
inout [ 7:0] ddr3_dqs_p;
|
||||
inout [ 7:0] ddr3_dqs_n;
|
||||
inout [ 63:0] ddr3_dq;
|
||||
output [ 7:0] ddr3_dm;
|
||||
input ddr3_rzq;
|
||||
input ddr3_ref_clk;
|
||||
// ad9361-interface
|
||||
|
||||
// ethernet
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [ 5:0] rx_data_in,
|
||||
output tx_clk_out,
|
||||
output tx_frame_out,
|
||||
output [ 5:0] tx_data_out,
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
input eth_ref_clk;
|
||||
input eth_rxd;
|
||||
output eth_txd;
|
||||
output eth_mdc;
|
||||
inout eth_mdio;
|
||||
output eth_resetn;
|
||||
input eth_intn;
|
||||
output gpio_resetb,
|
||||
output gpio_sync,
|
||||
output gpio_en_agc,
|
||||
output [ 3:0] gpio_ctl,
|
||||
input [ 7:0] gpio_status,
|
||||
|
||||
// board gpio
|
||||
|
||||
input [ 10:0] gpio_bd_i;
|
||||
output [ 15:0] gpio_bd_o;
|
||||
|
||||
// lane interface
|
||||
|
||||
input rx_ref_clk;
|
||||
input rx_sysref;
|
||||
output rx_sync;
|
||||
input [ 3:0] rx_data;
|
||||
input tx_ref_clk;
|
||||
input tx_sysref;
|
||||
input tx_sync;
|
||||
output [ 3:0] tx_data;
|
||||
|
||||
// gpio
|
||||
|
||||
input trig;
|
||||
input adc_fdb;
|
||||
input adc_fda;
|
||||
input dac_irq;
|
||||
input [ 1:0] clkd_status;
|
||||
output adc_pd;
|
||||
output dac_txen;
|
||||
output dac_reset;
|
||||
output clkd_sync;
|
||||
|
||||
// spi
|
||||
|
||||
output spi_csn_clk;
|
||||
output spi_csn_dac;
|
||||
output spi_csn_adc;
|
||||
output spi_clk;
|
||||
inout spi_sdio;
|
||||
output spi_dir;
|
||||
output spi_csn,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire eth_reset;
|
||||
wire eth_mdio_i;
|
||||
wire eth_mdio_o;
|
||||
wire eth_mdio_t;
|
||||
wire [ 63:0] gpio_i;
|
||||
wire [ 63:0] gpio_o;
|
||||
wire spi_miso_s;
|
||||
wire spi_mosi_s;
|
||||
wire [ 7:0] spi_csn_s;
|
||||
wire [ 31:0] gpio_i;
|
||||
wire [ 31:0] gpio_o;
|
||||
|
||||
// daq2
|
||||
// gpio (ad9361)
|
||||
|
||||
assign spi_csn_adc = spi_csn_s[2];
|
||||
assign spi_csn_dac = spi_csn_s[1];
|
||||
assign spi_csn_clk = spi_csn_s[0];
|
||||
assign gpio_i[31:24] = gpio_o[31:24];
|
||||
assign gpio_i[23:16] = gpio_status;
|
||||
|
||||
daq2_spi i_daq2_spi (
|
||||
.spi_csn (spi_csn_s[2:0]),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi_s),
|
||||
.spi_miso (spi_miso_s),
|
||||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
assign gpio_resetb = gpio_o[22];
|
||||
assign gpio_sync = gpio_o[21];
|
||||
assign gpio_en_agc = gpio_o[20];
|
||||
assign gpio_ctl = gpio_o[19:16];
|
||||
|
||||
// gpio in & out are separate cores
|
||||
// gpio (max-v-u21)
|
||||
|
||||
assign adc_pd = gpio_o[42];
|
||||
assign dac_txen = gpio_o[41];
|
||||
assign dac_reset = gpio_o[40];
|
||||
assign clkd_sync = gpio_o[38];
|
||||
assign gpio_i[15:8] = gpio_o[15:8];
|
||||
assign gpio_i[ 7:0] = gpio_bd_i;
|
||||
|
||||
assign gpio_i[63:38] = gpio_o[63:38];
|
||||
assign gpio_i[37:37] = trig;
|
||||
assign gpio_i[36:36] = adc_fdb;
|
||||
assign gpio_i[35:35] = adc_fda;
|
||||
assign gpio_i[34:34] = dac_irq;
|
||||
assign gpio_i[33:32] = clkd_status;
|
||||
assign gpio_bd_o = gpio_o[3:0];
|
||||
|
||||
// board stuff
|
||||
|
||||
assign eth_resetn = ~eth_reset;
|
||||
assign eth_mdio_i = eth_mdio;
|
||||
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
|
||||
|
||||
assign ddr3_a[14:12] = 3'd0;
|
||||
|
||||
assign gpio_i[31:27] = gpio_o[31:27];
|
||||
assign gpio_i[26:16] = gpio_bd_i;
|
||||
assign gpio_i[15: 0] = gpio_o[15:0];
|
||||
|
||||
assign gpio_bd_o = gpio_o[15:0];
|
||||
// instantiations
|
||||
|
||||
system_bd i_system_bd (
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
|
||||
.a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
|
||||
.a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
|
||||
.a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
|
||||
.a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
|
||||
.a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
|
||||
.a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
|
||||
.a10gx_base_sys_ethernet_reset_reset (eth_reset),
|
||||
.a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
|
||||
.a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
|
||||
.a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
|
||||
.a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
|
||||
.a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.a10gx_base_sys_spi_MISO (spi_miso_s),
|
||||
.a10gx_base_sys_spi_MOSI (spi_mosi_s),
|
||||
.a10gx_base_sys_spi_SCLK (spi_clk),
|
||||
.a10gx_base_sys_spi_SS_n (spi_csn_s),
|
||||
.daq2_rx_data_rx_serial_data (rx_data),
|
||||
.daq2_rx_ref_clk_clk (rx_ref_clk),
|
||||
.daq2_rx_sync_rx_sync (rx_sync),
|
||||
.daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
|
||||
.daq2_tx_data_tx_serial_data (tx_data),
|
||||
.daq2_tx_ref_clk_clk (tx_ref_clk),
|
||||
.daq2_tx_sync_tx_sync (tx_sync),
|
||||
.daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
|
||||
.ad9361_if_rx_clk_in_p (rx_clk_in),
|
||||
.ad9361_if_rx_clk_in_n (1'b0),
|
||||
.ad9361_if_rx_frame_in_p (rx_frame_in),
|
||||
.ad9361_if_rx_frame_in_n (1'b0),
|
||||
.ad9361_if_rx_data_in_p (rx_data_in),
|
||||
.ad9361_if_rx_data_in_n (6'd0),
|
||||
.ad9361_if_tx_clk_out_p (tx_clk_out),
|
||||
.ad9361_if_tx_clk_out_n (),
|
||||
.ad9361_if_tx_frame_out_p (tx_frame_out),
|
||||
.ad9361_if_tx_frame_out_n (),
|
||||
.ad9361_if_tx_data_out_p (tx_data_out),
|
||||
.ad9361_if_tx_data_out_n (),
|
||||
.ad9361_if_enable (enable),
|
||||
.ad9361_if_txnrx (txnrx),
|
||||
.delay_clk_clk (1'b0),
|
||||
.hps_ddr_mem_ck (hps_ddr_clk_p),
|
||||
.hps_ddr_mem_ck_n (hps_ddr_clk_n),
|
||||
.hps_ddr_mem_a (hsp_ddr_a),
|
||||
.hps_ddr_mem_act_n (hps_ddr_act_n),
|
||||
.hps_ddr_mem_ba (hps_ddr_ba),
|
||||
.hps_ddr_mem_bg (hps_ddr_bg),
|
||||
.hps_ddr_mem_cke (hps_ddr_cke),
|
||||
.hps_ddr_mem_cs_n (hps_ddr_cs_n),
|
||||
.hps_ddr_mem_odt (hps_ddr_odt),
|
||||
.hps_ddr_mem_reset_n (hps_ddr_reset_n),
|
||||
.hps_ddr_mem_par (hps_ddr_par),
|
||||
.hps_ddr_mem_alert_n (hps_ddr_alert_n),
|
||||
.hps_ddr_mem_dqs (hps_ddr_dqs_p),
|
||||
.hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
|
||||
.hps_ddr_mem_dq (hps_ddr_dq),
|
||||
.hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
|
||||
.hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
|
||||
.hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
|
||||
.hps_gpio_gp_in (gpio_i),
|
||||
.hps_gpio_gp_out (gpio_o),
|
||||
.hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
|
||||
.hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
|
||||
.hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
|
||||
.hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
|
||||
.hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
|
||||
.hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
|
||||
.hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
|
||||
.hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
|
||||
.hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
|
||||
.hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
|
||||
.hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
|
||||
.hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
|
||||
.hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
|
||||
.hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
|
||||
.hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
|
||||
.hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
|
||||
.hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
|
||||
.hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
|
||||
.hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
|
||||
.hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
|
||||
.hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
|
||||
.hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
|
||||
.hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
|
||||
.hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
|
||||
.hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
|
||||
.hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
|
||||
.hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
|
||||
.hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
|
||||
.hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
|
||||
.hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
|
||||
.hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
|
||||
.hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
|
||||
.hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
|
||||
.hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
|
||||
.hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
|
||||
.hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
|
||||
.hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
|
||||
.hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
|
||||
.hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
|
||||
.hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
|
||||
.hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
|
||||
.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
|
||||
.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
|
||||
.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
|
||||
.hps_spi0_mosi_o (spi_mosi),
|
||||
.hps_spi0_miso_i (spi_miso),
|
||||
.hps_spi0_ss_in_n (1'b1),
|
||||
.hps_spi0_mosi_oe (),
|
||||
.hps_spi0_ss0_n_o (spi_csn),
|
||||
.hps_spi0_ss1_n_o (),
|
||||
.hps_spi0_ss2_n_o (),
|
||||
.hps_spi0_ss3_n_o (),
|
||||
.hps_spi0_sclk_clk (spi_clk),
|
||||
.hps_spi1_mosi_o (),
|
||||
.hps_spi1_miso_i (1'b0),
|
||||
.hps_spi1_ss_in_n (1'b1),
|
||||
.hps_spi1_mosi_oe (),
|
||||
.hps_spi1_ss0_n_o (),
|
||||
.hps_spi1_ss1_n_o (),
|
||||
.hps_spi1_ss2_n_o (),
|
||||
.hps_spi1_ss3_n_o (),
|
||||
.hps_spi1_sclk_clk (),
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_reset_reset_n (sys_resetn));
|
||||
.sys_reset_reset_n (sys_resetn),
|
||||
.up_enable_up_enable (gpio_o[23]),
|
||||
.up_txnrx_up_txnrx (gpio_o[24]));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue