pzsdr1/pzsdr2- ccbox added tws
parent
5a7aa80145
commit
ddfbdfd2f7
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@ -97,6 +97,17 @@ module system_top (
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input [ 2:0] pss_valid_n,
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input [ 2:0] pss_valid_n,
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inout [ 2:0] adp5061_io,
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inout [ 2:0] adp5061_io,
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inout tsw_rot_com_a,
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inout tsw_dir_com_b,
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inout tsw_rot_s1,
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inout tsw_rot_a,
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inout tsw_rot_b,
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inout tsw_rot_misc,
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inout tsw_dir_s2,
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inout tsw_dir_s3,
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inout tsw_dir_s4,
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inout tsw_dir_s5,
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inout ltc2955_kill_n,
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inout ltc2955_kill_n,
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inout ltc2955_int_n,
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inout ltc2955_int_n,
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inout mic_present_n,
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inout mic_present_n,
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@ -204,11 +215,24 @@ module system_top (
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assign switch_led_b = gpio_o[0];
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assign switch_led_b = gpio_o[0];
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assign gpio_i[3:0] = gpio_o[3:0];
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assign gpio_i[3:0] = gpio_o[3:0];
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// ad9361 gpio - 63-32
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// ad9361 gpio - tact-scroll-wheel
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assign gpio_i[63:62] = gpio_o[63:62];
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ad_iobuf #(.DATA_WIDTH(10)) i_iobuf_tsw (
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assign gpio_i[60:57] = gpio_o[60:57];
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.dio_t ({gpio_t[63:62], gpio_t[60:57], gpio_t[50:47]}),
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assign gpio_i[50:47] = gpio_o[50:47];
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.dio_i ({gpio_o[63:62], gpio_o[60:57], gpio_o[50:47]}),
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.dio_o ({gpio_i[63:62], gpio_i[60:57], gpio_i[50:47]}),
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.dio_p ({ tsw_rot_com_a, // 63
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tsw_dir_com_b, // 62
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tsw_rot_s1, // 60
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tsw_rot_a, // 59
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tsw_rot_b, // 58
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tsw_rot_misc, // 57
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tsw_dir_s2, // 50
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tsw_dir_s3, // 49
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tsw_dir_s4, // 48
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tsw_dir_s5})); // 47
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// ad9361 gpio - 63-32
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ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
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ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
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.dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}),
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.dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}),
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@ -70,3 +70,16 @@ set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports pss_va
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set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[1]] ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N
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set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[1]] ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N
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set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[2]] ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N
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set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[2]] ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N
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## tsw
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set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports tsw_rot_com_a] ; ## U1,V16,IO_L18_34_JX4_P,JX4,68,TSW_COM_A
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set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports tsw_rot_s1] ; ## U1,W16,IO_L18_34_JX4_N,JX4,70,TSW_S1
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set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports tsw_rot_a] ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,TSW_A
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set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports tsw_rot_b] ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,TSW_B
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set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports tsw_rot_misc] ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,TSW_?
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set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports tsw_dir_com_b] ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,TSW_COM_B
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports tsw_dir_s2] ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,TSW_S2
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports tsw_dir_s3] ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,TSW_S3
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set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports tsw_dir_s4] ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,TSW_S4
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tsw_dir_s5] ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,TSW_S5
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@ -97,6 +97,17 @@ module system_top (
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input [ 2:0] pss_valid_n,
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input [ 2:0] pss_valid_n,
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inout [ 2:0] adp5061_io,
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inout [ 2:0] adp5061_io,
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inout tsw_rot_com_a,
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inout tsw_dir_com_b,
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inout tsw_rot_s1,
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inout tsw_rot_a,
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inout tsw_rot_b,
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inout tsw_rot_misc,
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inout tsw_dir_s2,
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inout tsw_dir_s3,
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inout tsw_dir_s4,
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inout tsw_dir_s5,
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inout otg_ctrl,
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inout otg_ctrl,
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inout adp1614_en,
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inout adp1614_en,
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inout ltc2955_kill_n,
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inout ltc2955_kill_n,
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@ -208,11 +219,24 @@ module system_top (
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assign switch_led_b = gpio_o[0];
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assign switch_led_b = gpio_o[0];
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assign gpio_i[3:0] = gpio_o[3:0];
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assign gpio_i[3:0] = gpio_o[3:0];
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// ad9361 gpio - 63-32
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// ad9361 gpio - tact-scroll-wheel
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assign gpio_i[63:62] = gpio_o[63:62];
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ad_iobuf #(.DATA_WIDTH(10)) i_iobuf_tsw (
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assign gpio_i[60:57] = gpio_o[60:57];
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.dio_t ({gpio_t[63:62], gpio_t[60:57], gpio_t[50:47]}),
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assign gpio_i[50:47] = gpio_o[50:47];
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.dio_i ({gpio_o[63:62], gpio_o[60:57], gpio_o[50:47]}),
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.dio_o ({gpio_i[63:62], gpio_i[60:57], gpio_i[50:47]}),
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.dio_p ({ tsw_rot_com_a, // 63
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tsw_dir_com_b, // 62
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tsw_rot_s1, // 60
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tsw_rot_a, // 59
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tsw_rot_b, // 58
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tsw_rot_misc, // 57
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tsw_dir_s2, // 50
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tsw_dir_s3, // 49
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tsw_dir_s4, // 48
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tsw_dir_s5})); // 47
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// ad9361 gpio - 63-32
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ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
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ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
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.dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}),
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.dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}),
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@ -70,6 +70,19 @@ set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports pss_va
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set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[1]] ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N
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set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[1]] ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N
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set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[2]] ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N
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set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[2]] ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N
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## tsw
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set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports tsw_rot_com_a] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,TSW_COM_A
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set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports tsw_rot_s1] ; ## U1,A7,IO_L18_34_JX4_N,JX4,70,TSW_S1
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports tsw_rot_a] ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,TSW_A
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set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports tsw_rot_b] ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,TSW_B
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports tsw_rot_misc] ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,TSW_?
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set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports tsw_dir_com_b] ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,TSW_COM_B
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set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports tsw_dir_s2] ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,TSW_S2
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports tsw_dir_s3] ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,TSW_S3
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set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports tsw_dir_s4] ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,TSW_S4
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set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports tsw_dir_s5] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,TSW_S5
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## misc
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## misc
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set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports otg_ctrl] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,OTG_CTRL
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set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports otg_ctrl] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,OTG_CTRL
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