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xilinx/common:ad_data_out.v: Fix typo

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Adrian Costina 2022-03-29 14:36:32 +01:00
parent 204dff3b73
commit de70157e3a
1 changed files with 1 additions and 1 deletions
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library/xilinx/common/ad_data_out.v
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@ -113,7 +113,7 @@ module ad_data_out #(
generate generate
if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
ODDR #(.DDR_CLK_EDGE ("IDDR_CLK_EDGE")) i_tx_data_oddr ( ODDR #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_tx_data_oddr (
.CE (1'b1), .CE (1'b1),
.R (1'b0), .R (1'b0),
.S (1'b0), .S (1'b0),