xilinx/common:ad_data_out.v: Fix typo

2022-03-29 14:36:32 +01:00 · 2022-03-29 14:36:32 +01:00 · de70157e3a
parent 204dff3b73
commit de70157e3a
1 changed files with 1 additions and 1 deletions
--- a/library/xilinx/common/ad_data_out.v
+++ b/library/xilinx/common/ad_data_out.v
@ -113,7 +113,7 @@ module ad_data_out #(

  generate
  if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
-  ODDR #(.DDR_CLK_EDGE ("IDDR_CLK_EDGE")) i_tx_data_oddr (
+  ODDR #(.DDR_CLK_EDGE (IDDR_CLK_EDGE)) i_tx_data_oddr (
    .CE (1'b1),
    .R (1'b0),
    .S (1'b0),