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Rejeesh Kutty 2015-01-09 11:12:56 -05:00
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// dma interface
dac_div_clk,
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [ 13:0] dac_data_out_a_p;
output [ 13:0] dac_data_out_a_n;
output [ 13:0] dac_data_out_b_p;
output [ 13:0] dac_data_out_b_n;
// dma interface
output dac_div_clk;
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [ 15:0] dac_data_00_s;
wire [ 15:0] dac_data_01_s;
wire [ 15:0] dac_data_02_s;
wire [ 15:0] dac_data_03_s;
wire [ 15:0] dac_data_04_s;
wire [ 15:0] dac_data_05_s;
wire [ 15:0] dac_data_06_s;
wire [ 15:0] dac_data_07_s;
wire [ 15:0] dac_data_08_s;
wire [ 15:0] dac_data_09_s;
wire [ 15:0] dac_data_10_s;
wire [ 15:0] dac_data_11_s;
wire [ 15:0] dac_data_12_s;
wire [ 15:0] dac_data_13_s;
wire [ 15:0] dac_data_14_s;
wire [ 15:0] dac_data_15_s;
wire dac_status_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9739a_if #(.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE)) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_rst (dac_rst),
.dac_clk (),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_data_00 (dac_data_00_s),
.dac_data_01 (dac_data_01_s),
.dac_data_02 (dac_data_02_s),
.dac_data_03 (dac_data_03_s),
.dac_data_04 (dac_data_04_s),
.dac_data_05 (dac_data_05_s),
.dac_data_06 (dac_data_06_s),
.dac_data_07 (dac_data_07_s),
.dac_data_08 (dac_data_08_s),
.dac_data_09 (dac_data_09_s),
.dac_data_10 (dac_data_10_s),
.dac_data_11 (dac_data_11_s),
.dac_data_12 (dac_data_12_s),
.dac_data_13 (dac_data_13_s),
.dac_data_14 (dac_data_14_s),
.dac_data_15 (dac_data_15_s));
// core
axi_ad9739a_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_data_00 (dac_data_00_s),
.dac_data_01 (dac_data_01_s),
.dac_data_02 (dac_data_02_s),
.dac_data_03 (dac_data_03_s),
.dac_data_04 (dac_data_04_s),
.dac_data_05 (dac_data_05_s),
.dac_data_06 (dac_data_06_s),
.dac_data_07 (dac_data_07_s),
.dac_data_08 (dac_data_08_s),
.dac_data_09 (dac_data_09_s),
.dac_data_10 (dac_data_10_s),
.dac_data_11 (dac_data_11_s),
.dac_data_12 (dac_data_12_s),
.dac_data_13 (dac_data_13_s),
.dac_data_14 (dac_data_14_s),
.dac_data_15 (dac_data_15_s),
.dac_status (dac_status_s),
.dac_valid (dac_valid),
.dac_enable (dac_enable),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a_channel (
// dac interface
dac_div_clk,
dac_rst,
dac_enable,
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15,
dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
input dac_rst;
output dac_enable;
output [ 15:0] dac_data_00;
output [ 15:0] dac_data_01;
output [ 15:0] dac_data_02;
output [ 15:0] dac_data_03;
output [ 15:0] dac_data_04;
output [ 15:0] dac_data_05;
output [ 15:0] dac_data_06;
output [ 15:0] dac_data_07;
output [ 15:0] dac_data_08;
output [ 15:0] dac_data_09;
output [ 15:0] dac_data_10;
output [ 15:0] dac_data_11;
output [ 15:0] dac_data_12;
output [ 15:0] dac_data_13;
output [ 15:0] dac_data_14;
output [ 15:0] dac_data_15;
input [255:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [ 15:0] dac_data_00 = 'd0;
reg [ 15:0] dac_data_01 = 'd0;
reg [ 15:0] dac_data_02 = 'd0;
reg [ 15:0] dac_data_03 = 'd0;
reg [ 15:0] dac_data_04 = 'd0;
reg [ 15:0] dac_data_05 = 'd0;
reg [ 15:0] dac_data_06 = 'd0;
reg [ 15:0] dac_data_07 = 'd0;
reg [ 15:0] dac_data_08 = 'd0;
reg [ 15:0] dac_data_09 = 'd0;
reg [ 15:0] dac_data_10 = 'd0;
reg [ 15:0] dac_data_11 = 'd0;
reg [ 15:0] dac_data_12 = 'd0;
reg [ 15:0] dac_data_13 = 'd0;
reg [ 15:0] dac_data_14 = 'd0;
reg [ 15:0] dac_data_15 = 'd0;
reg [ 15:0] dac_dds_phase_00_0 = 'd0;
reg [ 15:0] dac_dds_phase_00_1 = 'd0;
reg [ 15:0] dac_dds_phase_01_0 = 'd0;
reg [ 15:0] dac_dds_phase_01_1 = 'd0;
reg [ 15:0] dac_dds_phase_02_0 = 'd0;
reg [ 15:0] dac_dds_phase_02_1 = 'd0;
reg [ 15:0] dac_dds_phase_03_0 = 'd0;
reg [ 15:0] dac_dds_phase_03_1 = 'd0;
reg [ 15:0] dac_dds_phase_04_0 = 'd0;
reg [ 15:0] dac_dds_phase_04_1 = 'd0;
reg [ 15:0] dac_dds_phase_05_0 = 'd0;
reg [ 15:0] dac_dds_phase_05_1 = 'd0;
reg [ 15:0] dac_dds_phase_06_0 = 'd0;
reg [ 15:0] dac_dds_phase_06_1 = 'd0;
reg [ 15:0] dac_dds_phase_07_0 = 'd0;
reg [ 15:0] dac_dds_phase_07_1 = 'd0;
reg [ 15:0] dac_dds_phase_08_0 = 'd0;
reg [ 15:0] dac_dds_phase_08_1 = 'd0;
reg [ 15:0] dac_dds_phase_09_0 = 'd0;
reg [ 15:0] dac_dds_phase_09_1 = 'd0;
reg [ 15:0] dac_dds_phase_10_0 = 'd0;
reg [ 15:0] dac_dds_phase_10_1 = 'd0;
reg [ 15:0] dac_dds_phase_11_0 = 'd0;
reg [ 15:0] dac_dds_phase_11_1 = 'd0;
reg [ 15:0] dac_dds_phase_12_0 = 'd0;
reg [ 15:0] dac_dds_phase_12_1 = 'd0;
reg [ 15:0] dac_dds_phase_13_0 = 'd0;
reg [ 15:0] dac_dds_phase_13_1 = 'd0;
reg [ 15:0] dac_dds_phase_14_0 = 'd0;
reg [ 15:0] dac_dds_phase_14_1 = 'd0;
reg [ 15:0] dac_dds_phase_15_0 = 'd0;
reg [ 15:0] dac_dds_phase_15_1 = 'd0;
reg [ 15:0] dac_dds_incr_0 = 'd0;
reg [ 15:0] dac_dds_incr_1 = 'd0;
reg [ 15:0] dac_dds_data_00 = 'd0;
reg [ 15:0] dac_dds_data_01 = 'd0;
reg [ 15:0] dac_dds_data_02 = 'd0;
reg [ 15:0] dac_dds_data_03 = 'd0;
reg [ 15:0] dac_dds_data_04 = 'd0;
reg [ 15:0] dac_dds_data_05 = 'd0;
reg [ 15:0] dac_dds_data_06 = 'd0;
reg [ 15:0] dac_dds_data_07 = 'd0;
reg [ 15:0] dac_dds_data_08 = 'd0;
reg [ 15:0] dac_dds_data_09 = 'd0;
reg [ 15:0] dac_dds_data_10 = 'd0;
reg [ 15:0] dac_dds_data_11 = 'd0;
reg [ 15:0] dac_dds_data_12 = 'd0;
reg [ 15:0] dac_dds_data_13 = 'd0;
reg [ 15:0] dac_dds_data_14 = 'd0;
reg [ 15:0] dac_dds_data_15 = 'd0;
// internal signals
wire [ 15:0] dac_dds_data_00_s;
wire [ 15:0] dac_dds_data_01_s;
wire [ 15:0] dac_dds_data_02_s;
wire [ 15:0] dac_dds_data_03_s;
wire [ 15:0] dac_dds_data_04_s;
wire [ 15:0] dac_dds_data_05_s;
wire [ 15:0] dac_dds_data_06_s;
wire [ 15:0] dac_dds_data_07_s;
wire [ 15:0] dac_dds_data_08_s;
wire [ 15:0] dac_dds_data_09_s;
wire [ 15:0] dac_dds_data_10_s;
wire [ 15:0] dac_dds_data_11_s;
wire [ 15:0] dac_dds_data_12_s;
wire [ 15:0] dac_dds_data_13_s;
wire [ 15:0] dac_dds_data_14_s;
wire [ 15:0] dac_dds_data_15_s;
wire [ 15:0] dac_dds_scale_1_s;
wire [ 15:0] dac_dds_init_1_s;
wire [ 15:0] dac_dds_incr_1_s;
wire [ 15:0] dac_dds_scale_2_s;
wire [ 15:0] dac_dds_init_2_s;
wire [ 15:0] dac_dds_incr_2_s;
wire [ 15:0] dac_pat_data_1_s;
wire [ 15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
// dac data select
always @(posedge dac_div_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h2: begin
dac_data_00 <= dma_data[ 15: 0];
dac_data_01 <= dma_data[ 31: 16];
dac_data_02 <= dma_data[ 47: 32];
dac_data_03 <= dma_data[ 63: 48];
dac_data_04 <= dma_data[ 79: 64];
dac_data_05 <= dma_data[ 95: 80];
dac_data_06 <= dma_data[111: 96];
dac_data_07 <= dma_data[127:112];
dac_data_08 <= dma_data[143:128];
dac_data_09 <= dma_data[159:144];
dac_data_10 <= dma_data[175:160];
dac_data_11 <= dma_data[191:176];
dac_data_12 <= dma_data[207:192];
dac_data_13 <= dma_data[223:208];
dac_data_14 <= dma_data[239:224];
dac_data_15 <= dma_data[255:240];
end
4'h1: begin
dac_data_00 <= dac_pat_data_1_s;
dac_data_01 <= dac_pat_data_2_s;
dac_data_02 <= dac_pat_data_1_s;
dac_data_03 <= dac_pat_data_2_s;
dac_data_04 <= dac_pat_data_1_s;
dac_data_05 <= dac_pat_data_2_s;
dac_data_06 <= dac_pat_data_1_s;
dac_data_07 <= dac_pat_data_2_s;
dac_data_08 <= dac_pat_data_1_s;
dac_data_09 <= dac_pat_data_2_s;
dac_data_10 <= dac_pat_data_1_s;
dac_data_11 <= dac_pat_data_2_s;
dac_data_12 <= dac_pat_data_1_s;
dac_data_13 <= dac_pat_data_2_s;
dac_data_14 <= dac_pat_data_1_s;
dac_data_15 <= dac_pat_data_2_s;
end
default: begin
dac_data_00 <= dac_dds_data_00;
dac_data_01 <= dac_dds_data_01;
dac_data_02 <= dac_dds_data_02;
dac_data_03 <= dac_dds_data_03;
dac_data_04 <= dac_dds_data_04;
dac_data_05 <= dac_dds_data_05;
dac_data_06 <= dac_dds_data_06;
dac_data_07 <= dac_dds_data_07;
dac_data_08 <= dac_dds_data_08;
dac_data_09 <= dac_dds_data_09;
dac_data_10 <= dac_dds_data_10;
dac_data_11 <= dac_dds_data_11;
dac_data_12 <= dac_dds_data_12;
dac_data_13 <= dac_dds_data_13;
dac_data_14 <= dac_dds_data_14;
dac_data_15 <= dac_dds_data_15;
end
endcase
end
// single channel dds
always @(posedge dac_div_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_00_0 <= dac_dds_init_1_s;
dac_dds_phase_00_1 <= dac_dds_init_2_s;
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
dac_dds_data_00 <= 15'd0;
dac_dds_data_01 <= 15'd0;
dac_dds_data_02 <= 15'd0;
dac_dds_data_03 <= 15'd0;
dac_dds_data_04 <= 15'd0;
dac_dds_data_05 <= 15'd0;
dac_dds_data_06 <= 15'd0;
dac_dds_data_07 <= 15'd0;
dac_dds_data_08 <= 15'd0;
dac_dds_data_09 <= 15'd0;
dac_dds_data_10 <= 15'd0;
dac_dds_data_11 <= 15'd0;
dac_dds_data_12 <= 15'd0;
dac_dds_data_13 <= 15'd0;
dac_dds_data_14 <= 15'd0;
dac_dds_data_15 <= 15'd0;
end else begin
dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data_00 <= dac_dds_data_00_s;
dac_dds_data_01 <= dac_dds_data_01_s;
dac_dds_data_02 <= dac_dds_data_02_s;
dac_dds_data_03 <= dac_dds_data_03_s;
dac_dds_data_04 <= dac_dds_data_04_s;
dac_dds_data_05 <= dac_dds_data_05_s;
dac_dds_data_06 <= dac_dds_data_06_s;
dac_dds_data_07 <= dac_dds_data_07_s;
dac_dds_data_08 <= dac_dds_data_08_s;
dac_dds_data_09 <= dac_dds_data_09_s;
dac_dds_data_10 <= dac_dds_data_10_s;
dac_dds_data_11 <= dac_dds_data_11_s;
dac_dds_data_12 <= dac_dds_data_12_s;
dac_dds_data_13 <= dac_dds_data_13_s;
dac_dds_data_14 <= dac_dds_data_14_s;
dac_dds_data_15 <= dac_dds_data_15_s;
end
end
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_00_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_00_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_00_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_00_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_01_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_01_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_01_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_01_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_02_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_02_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_02_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_02_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_03_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_03_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_03_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_03_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_04_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_04_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_04_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_04_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_05_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_05_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_05_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_05_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_06_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_06_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_06_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_06_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_07_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_07_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_07_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_07_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_08_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_08_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_08_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_08_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_09_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_09_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_09_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_09_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_10_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_10_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_10_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_10_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_11_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_11_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_11_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_11_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_12_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_12_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_12_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_12_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_13_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_13_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_13_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_13_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_14_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_14_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_14_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_14_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_15_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_15_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_15_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_15_s));
end
endgenerate
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_ad9739a/axi_ad9739a_constr.xdc Executable file
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set_false_path -from [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *up_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *up_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]

253
library/axi_ad9739a/axi_ad9739a_core.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a_core (
// dac interface
dac_div_clk,
dac_rst,
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15,
dac_status,
// dma interface
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output [ 15:0] dac_data_00;
output [ 15:0] dac_data_01;
output [ 15:0] dac_data_02;
output [ 15:0] dac_data_03;
output [ 15:0] dac_data_04;
output [ 15:0] dac_data_05;
output [ 15:0] dac_data_06;
output [ 15:0] dac_data_07;
output [ 15:0] dac_data_08;
output [ 15:0] dac_data_09;
output [ 15:0] dac_data_10;
output [ 15:0] dac_data_11;
output [ 15:0] dac_data_12;
output [ 15:0] dac_data_13;
output [ 15:0] dac_data_14;
output [ 15:0] dac_data_15;
input dac_status;
// dma interface
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [ 31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
// defaults
assign dac_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s;
up_rack <= up_rack_s | up_rack_0_s;
up_wack <= up_wack_s | up_wack_0_s;
end
end
// dac channel
axi_ad9739a_channel #(
.CHID(0),
.DP_DISABLE(DP_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable),
.dac_data_00 (dac_data_00),
.dac_data_01 (dac_data_01),
.dac_data_02 (dac_data_02),
.dac_data_03 (dac_data_03),
.dac_data_04 (dac_data_04),
.dac_data_05 (dac_data_05),
.dac_data_06 (dac_data_06),
.dac_data_07 (dac_data_07),
.dac_data_08 (dac_data_08),
.dac_data_09 (dac_data_09),
.dac_data_10 (dac_data_10),
.dac_data_11 (dac_data_11),
.dac_data_12 (dac_data_12),
.dac_data_13 (dac_data_13),
.dac_data_14 (dac_data_14),
.dac_data_15 (dac_data_15),
.dma_data (dac_ddata),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.drp_clk (up_clk),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd1),
.drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd1),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9739a_if (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// internal resets and clocks
dac_rst,
dac_clk,
dac_div_clk,
dac_status,
// data interface
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15);
// parameters
parameter PCORE_DEVICE_TYPE = 0;
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// internal resets and clocks
input dac_rst;
output dac_clk;
output dac_div_clk;
output dac_status;
// data interface
input [15:0] dac_data_00;
input [15:0] dac_data_01;
input [15:0] dac_data_02;
input [15:0] dac_data_03;
input [15:0] dac_data_04;
input [15:0] dac_data_05;
input [15:0] dac_data_06;
input [15:0] dac_data_07;
input [15:0] dac_data_08;
input [15:0] dac_data_09;
input [15:0] dac_data_10;
input [15:0] dac_data_11;
input [15:0] dac_data_12;
input [15:0] dac_data_13;
input [15:0] dac_data_14;
input [15:0] dac_data_15;
// internal registers
reg dac_status = 'd0;
// internal signals
wire dac_clk_in_s;
wire dac_div_clk_s;
// dac status
always @(posedge dac_div_clk) begin
if (dac_rst == 1'b1) begin
dac_status <= 1'd0;
end else begin
dac_status <= 1'd1;
end
end
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
i_serdes_out_data_a (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_data_00[15:2]),
.data_s1 (dac_data_02[15:2]),
.data_s2 (dac_data_04[15:2]),
.data_s3 (dac_data_06[15:2]),
.data_s4 (dac_data_08[15:2]),
.data_s5 (dac_data_10[15:2]),
.data_s6 (dac_data_12[15:2]),
.data_s7 (dac_data_14[15:2]),
.data_out_p (dac_data_out_a_p),
.data_out_n (dac_data_out_a_n));
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
i_serdes_out_data_b (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_data_01[15:2]),
.data_s1 (dac_data_03[15:2]),
.data_s2 (dac_data_05[15:2]),
.data_s3 (dac_data_07[15:2]),
.data_s4 (dac_data_09[15:2]),
.data_s5 (dac_data_11[15:2]),
.data_s6 (dac_data_13[15:2]),
.data_s7 (dac_data_15[15:2]),
.data_out_p (dac_data_out_b_p),
.data_out_n (dac_data_out_b_n));
// dac clock output serdes & buffer
ad_serdes_out #(
.SERDES(1),
.DATA_WIDTH(1),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
.data_s3 (1'b0),
.data_s4 (1'b1),
.data_s5 (1'b0),
.data_s6 (1'b1),
.data_s7 (1'b0),
.data_out_p (dac_clk_out_p),
.data_out_n (dac_clk_out_n));
// dac clock input buffers
IBUFGDS i_dac_clk_in_ibuf (
.I (dac_clk_in_p),
.IB (dac_clk_in_n),
.O (dac_clk_in_s));
BUFG i_dac_clk_in_gbuf (
.I (dac_clk_in_s),
.O (dac_clk));
BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dac_clk_in_s),
.O (dac_div_clk_s));
BUFG i_dac_div_clk_gbuf (
.I (dac_div_clk_s),
.O (dac_div_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9739a
adi_ip_files axi_ad9739a [list \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"axi_ad9739a_channel.v" \
"axi_ad9739a_core.v" \
"axi_ad9739a_if.v" \
"axi_ad9739a_constr.xdc" \
"axi_ad9739a.v" ]
adi_ip_properties axi_ad9739a
adi_ip_constraints axi_ad9739a [list \
"axi_ad9739a_constr.xdc" ]
ipx::save_core [ipx::current_core]

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# dac interface
set dac_clk_in_p [create_bd_port -dir I dac_clk_in_p]
set dac_clk_in_n [create_bd_port -dir I dac_clk_in_n]
set dac_clk_out_p [create_bd_port -dir O dac_clk_out_p]
set dac_clk_out_n [create_bd_port -dir O dac_clk_out_n]
set dac_data_out_a_p [create_bd_port -dir O -from 13 -to 0 dac_data_out_a_p]
set dac_data_out_a_n [create_bd_port -dir O -from 13 -to 0 dac_data_out_a_n]
set dac_data_out_b_p [create_bd_port -dir O -from 13 -to 0 dac_data_out_b_p]
set dac_data_out_b_n [create_bd_port -dir O -from 13 -to 0 dac_data_out_b_n]
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
# interrupts
set ad9739a_dma_irq [create_bd_port -dir O ad9739a_dma_irq]
# dac peripherals
set axi_ad9739a [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9739a:1.0 axi_ad9739a]
set axi_ad9739a_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9739a_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_FIFO_SIZE {64}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9739a_dma
set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9739a_dma
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
# connections (dac)
connect_bd_net -net axi_ad9739a_dac_clk_in_p [get_bd_ports dac_clk_in_p] [get_bd_pins axi_ad9739a/dac_clk_in_p]
connect_bd_net -net axi_ad9739a_dac_clk_in_n [get_bd_ports dac_clk_in_n] [get_bd_pins axi_ad9739a/dac_clk_in_n]
connect_bd_net -net axi_ad9739a_dac_clk_out_p [get_bd_ports dac_clk_out_p] [get_bd_pins axi_ad9739a/dac_clk_out_p]
connect_bd_net -net axi_ad9739a_dac_clk_out_n [get_bd_ports dac_clk_out_n] [get_bd_pins axi_ad9739a/dac_clk_out_n]
connect_bd_net -net axi_ad9739a_dac_data_out_a_p [get_bd_ports dac_data_out_a_p] [get_bd_pins axi_ad9739a/dac_data_out_a_p]
connect_bd_net -net axi_ad9739a_dac_data_out_a_n [get_bd_ports dac_data_out_a_n] [get_bd_pins axi_ad9739a/dac_data_out_a_n]
connect_bd_net -net axi_ad9739a_dac_data_out_b_p [get_bd_ports dac_data_out_b_p] [get_bd_pins axi_ad9739a/dac_data_out_b_p]
connect_bd_net -net axi_ad9739a_dac_data_out_b_n [get_bd_ports dac_data_out_b_n] [get_bd_pins axi_ad9739a/dac_data_out_b_n]
connect_bd_net -net axi_ad9739a_dac_div_clk [get_bd_pins axi_ad9739a/dac_div_clk] [get_bd_pins axi_ad9739a_dma/fifo_rd_clk]
connect_bd_net -net axi_ad9739a_dac_valid [get_bd_pins axi_ad9739a/dac_valid] [get_bd_pins axi_ad9739a_dma/fifo_rd_en]
connect_bd_net -net axi_ad9739a_dac_ddata [get_bd_pins axi_ad9739a/dac_ddata] [get_bd_pins axi_ad9739a_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9739a_dac_dunf [get_bd_pins axi_ad9739a/dac_dunf] [get_bd_pins axi_ad9739a_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9739a_dma_irq [get_bd_pins axi_ad9739a_dma/irq] [get_bd_ports ad9739a_dma_irq]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9739a/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9739a_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9739a/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9739a_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9739a/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9739a_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
# interconnect (mem/dac)
set axi_ad9739a_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9739a_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9739a_dma_interconnect
connect_bd_intf_net -intf_net axi_ad9739a_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9739a_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9739a_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9739a_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9739a_dma/m_src_axi]
connect_bd_net -net axi_ad9739a_dac_div_clk [get_bd_pins axi_ad9739a_dma_interconnect/ACLK] [get_bd_pins axi_ad9739a/dac_div_clk]
connect_bd_net -net axi_ad9739a_dac_div_clk [get_bd_pins axi_ad9739a_dma_interconnect/M00_ACLK] [get_bd_pins axi_ad9739a/dac_div_clk]
connect_bd_net -net axi_ad9739a_dac_div_clk [get_bd_pins axi_ad9739a_dma_interconnect/S00_ACLK] [get_bd_pins axi_ad9739a/dac_div_clk]
connect_bd_net -net axi_ad9739a_dac_div_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net axi_ad9739a_dac_div_clk [get_bd_pins axi_ad9739a_dma/m_src_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9739a_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9739a_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9739a_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9739a_dma/m_src_axi_aresetn]
# spi
connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x74200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9739a/s_axi/axi_lite] SEG_data_ad9739a
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9739a_dma/s_axi/axi_lite] SEG_data_ad9739a_dma
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9739a_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad9739a_fmc_bd.tcl

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# ad9739a
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[0]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[0]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[1]] ; ## FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[1]] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[2]] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[2]] ; ## FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[3]] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[3]] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[4]] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[4]] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[5]] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[5]] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[6]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[6]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[7]] ; ## FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[8]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[8]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[9]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[9]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[10]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[11]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[11]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[12]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[13]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[13]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[0]] ; ## FMC_LPC_LA30_P
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[0]] ; ## FMC_LPC_LA30_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[1]] ; ## FMC_LPC_LA31_P
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[1]] ; ## FMC_LPC_LA31_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[2]] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[2]] ; ## FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[3]] ; ## FMC_LPC_LA29_P
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[3]] ; ## FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[4]] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[4]] ; ## FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[5]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[5]] ; ## FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[6]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[6]] ; ## FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[7]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[7]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[8]] ; ## FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[8]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[9]] ; ## FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[9]] ; ## FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[10]] ; ## FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[10]] ; ## FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[11]] ; ## FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[11]] ; ## FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[12]] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[12]] ; ## FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[13]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[13]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## FMC_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## FMC_LPC_LA32_P
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## FMC_LPC_LA33_N
# clocks
create_clock -name dac_clk_in -period 1.66 [get_ports dac_clk_in_p]
create_clock -name dac_div_clk -period 6.66 [get_pins i_system_wrapper/system_i/axi_ad9739a/dac_div_clk]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create ad9739a_fmc_zc706
adi_project_files ad9739a_fmc_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run ad9739a_fmc_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
spi_csn_clk,
spi_csn_dac,
spi_clk,
spi_mosi,
spi_miso);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
output spi_csn_clk;
output spi_csn_dac;
output spi_clk;
output spi_mosi;
input spi_miso;
// internal signals
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire [15:0] ps_intrs;
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd (
.dt (gpio_t[14:0]),
.di (gpio_o[14:0]),
.do (gpio_i[14:0]),
.dio (gpio_bd));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ad9739a_dma_irq (ps_intrs[12]),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_data_out_b_p (dac_data_out_b_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.spdif (spdif),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_0_o (spi_csn_clk),
.spi_csn_1_o (spi_csn_dac),
.spi_csn_i (1'b1),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************