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axi_dacfifo: Data from DMA is validated with dma_ready too

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Istvan Csomortani 2017-02-24 12:32:25 +02:00
parent dfcd5214a0
commit debc6e2066
1 changed files with 1 additions and 1 deletions
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library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
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@ -333,7 +333,7 @@ module axi_dacfifo_wr (
(MEM_RATIO == 8) ? {dma_mem_raddr, 3'b0} :
{dma_mem_raddr, 4'b0};
assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1];
assign dma_mem_wea_s = dma_xfer_req & dma_valid;
assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst_s == 1'b1) begin