From dee108ba224c007f784a011c0d4189ab0d4e9863 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 12 Jan 2021 09:19:13 +0000 Subject: [PATCH] fmcomms8/intel: Fix fPLL configuration When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel. --- projects/fmcomms8/a10soc/system_constr.sdc | 8 ++++---- projects/fmcomms8/common/fmcomms8_qsys.tcl | 20 ++++++++++++-------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/projects/fmcomms8/a10soc/system_constr.sdc b/projects/fmcomms8/a10soc/system_constr.sdc index 7ba3779c9..6b4df93c2 100755 --- a/projects/fmcomms8/a10soc/system_constr.sdc +++ b/projects/fmcomms8/a10soc/system_constr.sdc @@ -1,9 +1,9 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "4.069 ns" -name ref_clk_c [get_ports {ref_clk_c}] -create_clock -period "4.069 ns" -name ref_clk_d [get_ports {ref_clk_d}] -create_clock -period "4.069 ns" -name core_clk_c [get_ports {core_clk_c}] -create_clock -period "4.069 ns" -name core_clk_d [get_ports {core_clk_d}] +create_clock -period "4.06504065 ns" -name ref_clk_c [get_ports {ref_clk_c}] +create_clock -period "4.06504065 ns" -name ref_clk_d [get_ports {ref_clk_d}] +create_clock -period "4.06504065 ns" -name core_clk_c [get_ports {core_clk_c}] +create_clock -period "4.06504065 ns" -name core_clk_d [get_ports {core_clk_d}] create_clock -period "100 ns" -name spi_clk [get_nets {i_system_bd|sys_spi|sys_spi|SCLK_reg}] derive_pll_clocks diff --git a/projects/fmcomms8/common/fmcomms8_qsys.tcl b/projects/fmcomms8/common/fmcomms8_qsys.tcl index 34e12e71f..ae64344a8 100644 --- a/projects/fmcomms8/common/fmcomms8_qsys.tcl +++ b/projects/fmcomms8/common/fmcomms8_qsys.tcl @@ -27,13 +27,17 @@ set dac_fifo_name avl_fmcomms8_tx_fifo set dac_data_width 256 set dac_dma_data_width 256 +# NOTE: The real lane rate is 9830.4 Gbps (Tx/Rx/Rx_Obs), with a real reference +# clock frequency of 245.76 MHz. A round up needed because the fPLL's configuration +# interface does not support fractional numbers. + # JESD204B/C clock bridges add_instance core_clk_c altera_clock_bridge - set_instance_parameter_value core_clk_c {EXPLICIT_CLOCK_RATE} {245760000} + set_instance_parameter_value core_clk_c {EXPLICIT_CLOCK_RATE} {246000000} add_instance core_clk_d altera_clock_bridge - set_instance_parameter_value core_clk_d {EXPLICIT_CLOCK_RATE} {245760000} + set_instance_parameter_value core_clk_d {EXPLICIT_CLOCK_RATE} {246000000} # fmcomms8_tx JESD204 @@ -41,8 +45,8 @@ add_instance fmcomms8_tx_jesd204 adi_jesd204 set_instance_parameter_value fmcomms8_tx_jesd204 {ID} {0} set_instance_parameter_value fmcomms8_tx_jesd204 {TX_OR_RX_N} {1} set_instance_parameter_value fmcomms8_tx_jesd204 {SOFT_PCS} {true} -set_instance_parameter_value fmcomms8_tx_jesd204 {LANE_RATE} {9830.4} -set_instance_parameter_value fmcomms8_tx_jesd204 {REFCLK_FREQUENCY} {245.76} +set_instance_parameter_value fmcomms8_tx_jesd204 {LANE_RATE} {9840} +set_instance_parameter_value fmcomms8_tx_jesd204 {REFCLK_FREQUENCY} {246} set_instance_parameter_value fmcomms8_tx_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES set_instance_parameter_value fmcomms8_tx_jesd204 {LANE_MAP} {1 0 2 3 4 5 6 7} set_instance_parameter_value fmcomms8_tx_jesd204 {EXT_DEVICE_CLK_EN} {1} @@ -64,8 +68,8 @@ add_instance fmcomms8_rx_jesd204 adi_jesd204 set_instance_parameter_value fmcomms8_rx_jesd204 {ID} {1} set_instance_parameter_value fmcomms8_rx_jesd204 {TX_OR_RX_N} {0} set_instance_parameter_value fmcomms8_rx_jesd204 {SOFT_PCS} {true} -set_instance_parameter_value fmcomms8_rx_jesd204 {LANE_RATE} {9830.4} -set_instance_parameter_value fmcomms8_rx_jesd204 {REFCLK_FREQUENCY} {245.76} +set_instance_parameter_value fmcomms8_rx_jesd204 {LANE_RATE} {9840} +set_instance_parameter_value fmcomms8_rx_jesd204 {REFCLK_FREQUENCY} {246} set_instance_parameter_value fmcomms8_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES set_instance_parameter_value fmcomms8_rx_jesd204 {EXT_DEVICE_CLK_EN} {1} @@ -86,8 +90,8 @@ add_instance fmcomms8_rx_os_jesd204 adi_jesd204 set_instance_parameter_value fmcomms8_rx_os_jesd204 {ID} {1} set_instance_parameter_value fmcomms8_rx_os_jesd204 {TX_OR_RX_N} {0} set_instance_parameter_value fmcomms8_rx_os_jesd204 {SOFT_PCS} {true} -set_instance_parameter_value fmcomms8_rx_os_jesd204 {LANE_RATE} {9830.4} -set_instance_parameter_value fmcomms8_rx_os_jesd204 {REFCLK_FREQUENCY} {245.76} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {LANE_RATE} {9840} +set_instance_parameter_value fmcomms8_rx_os_jesd204 {REFCLK_FREQUENCY} {246} set_instance_parameter_value fmcomms8_rx_os_jesd204 {NUM_OF_LANES} $RX_OS_NUM_OF_LANES set_instance_parameter_value fmcomms8_rx_os_jesd204 {EXT_DEVICE_CLK_EN} {1}