From df88b33946d5cfa9eeb99320bae0b72f176813aa Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 2 Oct 2015 09:30:31 +0300 Subject: [PATCH] usb_fx3: Initial commit Only the UART connections are available. The FMC should not be populated at this time --- projects/usb_fx3/common/usb_fx3_bd.tcl | 82 +++++++++ projects/usb_fx3/zc706/system_bd.tcl | 4 + projects/usb_fx3/zc706/system_constr.xdc | 65 +++++++ projects/usb_fx3/zc706/system_project.tcl | 14 ++ projects/usb_fx3/zc706/system_top.v | 215 ++++++++++++++++++++++ 5 files changed, 380 insertions(+) create mode 100644 projects/usb_fx3/common/usb_fx3_bd.tcl create mode 100644 projects/usb_fx3/zc706/system_bd.tcl create mode 100644 projects/usb_fx3/zc706/system_constr.xdc create mode 100644 projects/usb_fx3/zc706/system_project.tcl create mode 100644 projects/usb_fx3/zc706/system_top.v diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl new file mode 100644 index 000000000..0f1ec53ba --- /dev/null +++ b/projects/usb_fx3/common/usb_fx3_bd.tcl @@ -0,0 +1,82 @@ + +create_bd_port -dir I usb_fx3_uart_tx +create_bd_port -dir O usb_fx3_uart_rx + +create_bd_port -dir I dma_rdy +create_bd_port -dir I dma_wmk +create_bd_port -dir I -from 10 -to 0 fifo_rdy +create_bd_port -dir O pclk +create_bd_port -dir O -from 31 -to 0 data +create_bd_port -dir O -from 4 -to 0 addr +create_bd_port -dir O slcs_n +create_bd_port -dir O slrd_n +create_bd_port -dir O sloe_n +create_bd_port -dir O slwr_n +create_bd_port -dir O pktend_n +create_bd_port -dir O epswitch_n + +set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7 + +#set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3] + +#set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma] +#set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma + +#ad_connect axi_usb_fx3_dma/S_AXIS_S2MM axi_usb_fx3/m_axis +#ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S + +ad_connect /sys_ps7/UART0_RX usb_fx3_uart_tx +ad_connect /sys_ps7/UART0_TX usb_fx3_uart_rx + +#ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk +#ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn + +#ad_connect axi_usb_fx3/dma_rdy dma_rdy +#ad_connect axi_usb_fx3/dma_wmk dma_wmk +#ad_connect axi_usb_fx3/fifo_rdy fifo_rdy +#ad_connect axi_usb_fx3/pclk pclk +#ad_connect axi_usb_fx3/data data +#ad_connect axi_usb_fx3/addr addr +#ad_connect axi_usb_fx3/slcs_n slcs_n +#ad_connect axi_usb_fx3/slrd_n slrd_n +#ad_connect axi_usb_fx3/sloe_n sloe_n +#ad_connect axi_usb_fx3/slwr_n slwr_n +#ad_connect axi_usb_fx3/pktend_n pktend_n +#ad_connect axi_usb_fx3/epswitch_n epswitch_n + +#ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq +#ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut +#ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut + +#ad_cpu_interconnect 0x50000000 axi_usb_fx3 +#ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma +#ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +#ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG +#ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S +#ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM + +# test + +#set vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc] +#ad_connect vcc/dout axi_usb_fx3/m_axis_tready +# +#set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila] +#set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila +#set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila +#set_property -dict [list CONFIG.C_PROBE1_WIDTH {4}] $ila +#set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila +#set_property -dict [list CONFIG.C_DATA_DEPTH {32768}] $ila +#set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila +#set_property -dict [list CONFIG.C_PROBE3_MU_CNT {2} ] $ila +#set_property -dict [list CONFIG.C_PROBE2_MU_CNT {2}] $ila +#set_property -dict [list CONFIG.C_PROBE1_MU_CNT {2}] $ila +#set_property -dict [list CONFIG.C_PROBE0_MU_CNT {2}] $ila +#set_property -dict [list CONFIG.ALL_PROBE_SAME_MU_CNT {2}] $ila +#set_property -dict [list CONFIG.C_ENABLE_ILA_AXI_MON {false}] $ila +# +#ad_connect ila/clk axi_usb_fx3/pclk +#ad_connect ila/probe0 axi_usb_fx3/m_axis_tdata +#ad_connect ila/probe1 axi_usb_fx3/m_axis_tkeep +#ad_connect ila/probe2 axi_usb_fx3/m_axis_tlast +#ad_connect ila/probe3 axi_usb_fx3/m_axis_tvalid +# diff --git a/projects/usb_fx3/zc706/system_bd.tcl b/projects/usb_fx3/zc706/system_bd.tcl new file mode 100644 index 000000000..319b8dd75 --- /dev/null +++ b/projects/usb_fx3/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/usb_fx3/common/usb_fx3_bd.tcl + diff --git a/projects/usb_fx3/zc706/system_constr.xdc b/projects/usb_fx3/zc706/system_constr.xdc new file mode 100644 index 000000000..c425d3f2d --- /dev/null +++ b/projects/usb_fx3/zc706/system_constr.xdc @@ -0,0 +1,65 @@ + +# constraints +# USB_FX3 + +#set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports data[0]] ; ## H04 FMC_LPC_CLK0_M2C_P +#set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports data[1]] ; ## H07 FMC_LPC_LA02_P +#set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports data[2]] ; ## H08 FMC_LPC_LA02_N +#set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports data[3]] ; ## H10 FMC_LPC_LA04_P +#set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS33} [get_ports data[4]] ; ## H11 FMC_LPC_LA04_N +#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports data[5]] ; ## H13 FMC_LPC_LA07_P +#set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33} [get_ports data[6]] ; ## H14 FMC_LPC_LA07_N +#set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS33} [get_ports data[7]] ; ## H16 FMC_LPC_LA11_P +#set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS33} [get_ports data[8]] ; ## H17 FMC_LPC_LA11_N +#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS33} [get_ports data[9]] ; ## H19 FMC_LPC_LA15_P +#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS33} [get_ports data[10]] ; ## H20 FMC_LPC_LA15_N +#set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports data[11]] ; ## H22 FMC_LPC_LA19_P +#set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS33} [get_ports data[12]] ; ## H23 FMC_LPC_LA19_N +#set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports data[13]] ; ## H25 FMC_LPC_LA21_P +#set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports data[14]] ; ## H26 FMC_LPC_LA21_N +#set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS33} [get_ports data[15]] ; ## H28 FMC_LPC_LA24_P +#set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports data[16]] ; ## H29 FMC_LPC_LA24_N +#set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports data[17]] ; ## H31 FMC_LPC_LA28_P +#set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports data[18]] ; ## H32 FMC_LPC_LA28_N +#set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS33} [get_ports data[19]] ; ## H34 FMC_LPC_LA30_P +#set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS33} [get_ports data[20]] ; ## H35 FMC_LPC_LA30_N +#set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports data[21]] ; ## H37 FMC_LPC_LA32_P +#set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS33} [get_ports data[22]] ; ## H38 FMC_LPC_LA32_N +#set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVCMOS33} [get_ports data[23]] ; ## G02 FMC_LPC_CLK1_M2C_P +#set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports data[24]] ; ## G03 FMC_LPC_CLK1_M2C_N +#set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports data[25]] ; ## G09 FMC_LPC_LA03_P +#set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS33} [get_ports data[26]] ; ## G10 FMC_LPC_LA03_N +#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports data[27]] ; ## G12 FMC_LPC_LA08_P +#set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports data[28]] ; ## G13 FMC_LPC_LA08_N +#set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS33} [get_ports data[29]] ; ## G15 FMC_LPC_LA12_P +#set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS33} [get_ports data[30]] ; ## G16 FMC_LPC_LA12_N +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports data[31]] ; ## G18 FMC_LPC_LA16_P +# +#set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports pclk] ; ## G06 FMC_LPC_LA00_CC_P +# +#set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS33} [get_ports addr[0]] ; ## G37 FMC_LPC_LA33_N +#set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS33} [get_ports addr[1]] ; ## G36 FMC_LPC_LA33_P +#set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS33} [get_ports addr[2]] ; ## G34 FMC_LPC_LA31_N +#set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS33} [get_ports addr[3]] ; ## G33 FMC_LPC_LA31_P +#set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports addr[4]] ; ## G31 FMC_LPC_LA29_N +# +#set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports slcs_n] ; ## G19 FMC_LPC_LA16_N +#set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports slwr_n] ; ## G21 FMC_LPC_LA20_P +#set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports sloe_n] ; ## G22 FMC_LPC_LA20_N +#set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports slrd_n] ; ## G24 FMC_LPC_LA22_P +#set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports pktend_n] ; ## G30 FMC_LPC_LA29_P + +set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx] ; ## PMOD1_0, Connector J58 pin 1, 3.3V through level shifter +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx] ; ## PMOD1_4, Connector J58 pin 2, 3.3V through level shifter + +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[0]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[1]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[2]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[3]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[4]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[5]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[6]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[7]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[8]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[9]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[10]] ; ## G18 FMC_LPC_LA16_P diff --git a/projects/usb_fx3/zc706/system_project.tcl b/projects/usb_fx3/zc706/system_project.tcl new file mode 100644 index 000000000..8bfc00965 --- /dev/null +++ b/projects/usb_fx3/zc706/system_project.tcl @@ -0,0 +1,14 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create usb_fx3_zc706 +adi_project_files usb_fx3_zc706 [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v"] + +adi_project_run usb_fx3_zc706 + diff --git a/projects/usb_fx3/zc706/system_top.v b/projects/usb_fx3/zc706/system_top.v new file mode 100644 index 000000000..d21458d0f --- /dev/null +++ b/projects/usb_fx3/zc706/system_top.v @@ -0,0 +1,215 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + usb_fx3_uart_tx, + usb_fx3_uart_rx, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [14:0] gpio_bd; + + input usb_fx3_uart_tx; + output usb_fx3_uart_rx; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire usb_fx3_uart_tx; + wire usb_fx3_uart_rx; + wire dma_rdy; + wire dma_wmk; + wire [10:0] fifo_rdy; + wire pclk; + wire [31:0] data; + wire [4:0] addr; + wire slcs_n; + wire slrd_n; + wire sloe_n; + wire slwr_n; + wire epswitch_n; + wire pktend_n; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(15) + ) i_gpio_bd ( + .dio_t(gpio_t[14:0]), + .dio_i(gpio_o[14:0]), + .dio_o(gpio_i[14:0]), + .dio_p(gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .usb_fx3_uart_tx(usb_fx3_uart_tx), + .usb_fx3_uart_rx(usb_fx3_uart_rx), + .dma_rdy(dma_rdy), + .dma_wmk(dma_wmk), + .fifo_rdy(fifo_rdy), + .pclk(pclk), + .data(data), + .addr(addr), + .slcs_n(slcs_n), + .slrd_n(slrd_n), + .sloe_n(sloe_n), + .slwr_n(slwr_n), + .epswitch_n(epswitch_n), + .pktend_n(pktend_n), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************