zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_ad9671: Updated constraints

main
Adrian Costina 2015-10-09 13:15:55 +03:00
parent 03b225a802
commit df8ac2e726
3 changed files with 3 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
library/axi_ad9671/Makefile
View File

@ -18,6 +18,7 @@ M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/ad_mem.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += axi_ad9671_pnmon.v
M_DEPS += axi_ad9671_channel.v
M_DEPS += axi_ad9671_if.v

43
library/axi_ad9671/axi_ad9671_constr.xdc
View File

@ -1,44 +1 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9671_clk [get_clocks -of_objects [get_ports rx_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9671_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

2
library/axi_ad9671/axi_ad9671_ip.tcl
View File

@ -15,6 +15,7 @@ adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9671_pnmon.v" \
"axi_ad9671_channel.v" \
"axi_ad9671_if.v" \
@ -24,6 +25,7 @@ adi_ip_files axi_ad9671 [list \
adi_ip_properties axi_ad9671
adi_ip_constraints axi_ad9671 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9671_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]