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motor_control: Modified foc_controller to be compatible with other cores

main
Adrian Costina 2014-09-03 12:09:37 +03:00
parent 9f3461b130
commit dfb94f7b68
3 changed files with 70 additions and 66 deletions
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116
library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.v
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@ -34,17 +34,17 @@ module controllerperipheralhdladi_pcore
encoder_a,
encoder_b,
encoder_index,
AXI_Lite_ACLK,
AXI_Lite_ARESETN,
AXI_Lite_AWADDR,
AXI_Lite_AWVALID,
AXI_Lite_WDATA,
AXI_Lite_WSTRB,
AXI_Lite_WVALID,
AXI_Lite_BREADY,
AXI_Lite_ARADDR,
AXI_Lite_ARVALID,
AXI_Lite_RREADY,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_rready,
pwm_a,
pwm_b,
pwm_c,
@ -57,16 +57,18 @@ module controllerperipheralhdladi_pcore
mon_rotor_velocity,
mon_d_current,
mon_q_current,
AXI_Lite_AWREADY,
AXI_Lite_WREADY,
AXI_Lite_BRESP,
AXI_Lite_BVALID,
AXI_Lite_ARREADY,
AXI_Lite_RDATA,
AXI_Lite_RRESP,
AXI_Lite_RVALID
s_axi_awready,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid
);
parameter C_BASEADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
input IPCORE_CLK; // ufix1
input IPCORE_RESETN; // ufix1
@ -75,17 +77,17 @@ module controllerperipheralhdladi_pcore
input encoder_a; // ufix1
input encoder_b; // ufix1
input encoder_index; // ufix1
input AXI_Lite_ACLK; // ufix1
input AXI_Lite_ARESETN; // ufix1
input [31:0] AXI_Lite_AWADDR; // ufix32
input AXI_Lite_AWVALID; // ufix1
input [31:0] AXI_Lite_WDATA; // ufix32
input [3:0] AXI_Lite_WSTRB; // ufix4
input AXI_Lite_WVALID; // ufix1
input AXI_Lite_BREADY; // ufix1
input [31:0] AXI_Lite_ARADDR; // ufix32
input AXI_Lite_ARVALID; // ufix1
input AXI_Lite_RREADY; // ufix1
input s_axi_aclk; // ufix1
input s_axi_aresetn; // ufix1
input [31:0] s_axi_awaddr; // ufix32
input s_axi_awvalid; // ufix1
input [31:0] s_axi_wdata; // ufix32
input [3:0] s_axi_wstrb; // ufix4
input s_axi_wvalid; // ufix1
input s_axi_bready; // ufix1
input [31:0] s_axi_araddr; // ufix32
input s_axi_arvalid; // ufix1
input s_axi_rready; // ufix1
output pwm_a; // ufix1
output pwm_b; // ufix1
output pwm_c; // ufix1
@ -98,14 +100,14 @@ module controllerperipheralhdladi_pcore
output [31:0] mon_rotor_velocity; // ufix32
output [31:0] mon_d_current; // ufix32
output [31:0] mon_q_current; // ufix32
output AXI_Lite_AWREADY; // ufix1
output AXI_Lite_WREADY; // ufix1
output [1:0] AXI_Lite_BRESP; // ufix2
output AXI_Lite_BVALID; // ufix1
output AXI_Lite_ARREADY; // ufix1
output [31:0] AXI_Lite_RDATA; // ufix32
output [1:0] AXI_Lite_RRESP; // ufix2
output AXI_Lite_RVALID; // ufix1
output s_axi_awready; // ufix1
output s_axi_wready; // ufix1
output [1:0] s_axi_bresp; // ufix2
output s_axi_bvalid; // ufix1
output s_axi_arready; // ufix1
output [31:0] s_axi_rdata; // ufix32
output [1:0] s_axi_rresp; // ufix2
output s_axi_rvalid; // ufix1
wire reset;
@ -147,26 +149,26 @@ module controllerperipheralhdladi_pcore
controllerperipheralhdladi_pcore_axi_lite u_controllerperipheralhdladi_pcore_axi_lite_inst (.reset(reset),
.AXI_Lite_ACLK(AXI_Lite_ACLK), // ufix1
.AXI_Lite_ARESETN(AXI_Lite_ARESETN), // ufix1
.AXI_Lite_AWADDR(AXI_Lite_AWADDR), // ufix32
.AXI_Lite_AWVALID(AXI_Lite_AWVALID), // ufix1
.AXI_Lite_WDATA(AXI_Lite_WDATA), // ufix32
.AXI_Lite_WSTRB(AXI_Lite_WSTRB), // ufix4
.AXI_Lite_WVALID(AXI_Lite_WVALID), // ufix1
.AXI_Lite_BREADY(AXI_Lite_BREADY), // ufix1
.AXI_Lite_ARADDR(AXI_Lite_ARADDR), // ufix32
.AXI_Lite_ARVALID(AXI_Lite_ARVALID), // ufix1
.AXI_Lite_RREADY(AXI_Lite_RREADY), // ufix1
.AXI_Lite_ACLK(s_axi_aclk), // ufix1
.AXI_Lite_ARESETN(s_axi_aresetn), // ufix1
.AXI_Lite_AWADDR(s_axi_awaddr), // ufix32
.AXI_Lite_AWVALID(s_axi_awvalid), // ufix1
.AXI_Lite_WDATA(s_axi_wdata), // ufix32
.AXI_Lite_WSTRB(s_axi_wstrb), // ufix4
.AXI_Lite_WVALID(s_axi_wvalid), // ufix1
.AXI_Lite_BREADY(s_axi_bready), // ufix1
.AXI_Lite_ARADDR(s_axi_araddr), // ufix32
.AXI_Lite_ARVALID(s_axi_arvalid), // ufix1
.AXI_Lite_RREADY(s_axi_rready), // ufix1
.read_axi_electrical_pos_err(axi_electrical_pos_err_sig), // sfix19_En14
.AXI_Lite_AWREADY(AXI_Lite_AWREADY), // ufix1
.AXI_Lite_WREADY(AXI_Lite_WREADY), // ufix1
.AXI_Lite_BRESP(AXI_Lite_BRESP), // ufix2
.AXI_Lite_BVALID(AXI_Lite_BVALID), // ufix1
.AXI_Lite_ARREADY(AXI_Lite_ARREADY), // ufix1
.AXI_Lite_RDATA(AXI_Lite_RDATA), // ufix32
.AXI_Lite_RRESP(AXI_Lite_RRESP), // ufix2
.AXI_Lite_RVALID(AXI_Lite_RVALID), // ufix1
.AXI_Lite_AWREADY(s_axi_awready), // ufix1
.AXI_Lite_WREADY(s_axi_wready), // ufix1
.AXI_Lite_BRESP(s_axi_bresp), // ufix2
.AXI_Lite_BVALID(s_axi_bvalid), // ufix1
.AXI_Lite_ARREADY(s_axi_arready), // ufix1
.AXI_Lite_RDATA(s_axi_rdata), // ufix32
.AXI_Lite_RRESP(s_axi_rresp), // ufix2
.AXI_Lite_RVALID(s_axi_rvalid), // ufix1
.write_axi_enable(dut_enable), // ufix1
.write_axi_controller_mode(axi_controller_mode_sig), // ufix2
.write_axi_command(axi_command_sig), // sfix18_En8

6
library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore.tcl → library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_ip.tcl
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@ -111,6 +111,10 @@ adi_ip_files controllerperipheralhdladi_pcore [list \
adi_ip_properties controllerperipheralhdladi_pcore
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
ipx::remove_bus_interface {signal_clock} [ipx::current_core]
ipx::save_core [ipx::current_core]

14
projects/motor_control/common/motor_control_bd.tcl
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@ -221,9 +221,7 @@
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_controller/position_i]
connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o]
connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o]
connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk]
connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en]
connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din]
@ -282,15 +280,15 @@
connect_bd_net -net util_adc_pack_0_dsync [get_bd_pins axi_controller_dma/fifo_wr_sync] [get_bd_pins util_adc_pack_0/dsync]
#foc_controller
connect_bd_net -net sys_100m_clk [get_bd_pins foc_controller/AXI_Lite_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins foc_controller/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_ps7_FCLK_CLK2 [get_bd_pins foc_controller/IPCORE_CLK] [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/AXI_Lite_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/IPCORE_RESETN] $sys_100m_resetn_source
connect_bd_net -net foc_controller_mon_d_current [get_bd_pins axi_mc_controller/ctrl_data6_i]
connect_bd_net -net foc_controller_mon_d_current [get_bd_pins foc_controller/mon_d_current]
connect_bd_net -net foc_controller_pwm_a [get_bd_pins axi_mc_controller/pwm_a_i] [get_bd_pins foc_controller/pwm_a]
connect_bd_net -net foc_controller_pwm_b [get_bd_pins axi_mc_controller/pwm_b_i] [get_bd_pins foc_controller/pwm_b]
connect_bd_net -net foc_controller_pwm_c [get_bd_pins axi_mc_controller/pwm_c_i] [get_bd_pins foc_controller/pwm_c]
@ -342,7 +340,7 @@
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_controller_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins foc_controller/AXI_Lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins foc_controller/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
@ -444,7 +442,7 @@
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/AXI_Lite/reg0] SEG_foc_controller_reg0
create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm