axi_ad9652: Updated with the latest constraints

main
Adrian Costina 2015-09-28 11:29:07 +03:00
parent 046c89dacd
commit dff6c0df01
4 changed files with 10 additions and 48 deletions

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@ -22,6 +22,7 @@ M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += axi_ad9652_pnmon.v M_DEPS += axi_ad9652_pnmon.v
M_DEPS += axi_ad9652_channel.v M_DEPS += axi_ad9652_channel.v
M_DEPS += axi_ad9652_if.v M_DEPS += axi_ad9652_if.v

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@ -1,9 +1,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2011(c) Analog Devices, Inc.
// //
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without modification, // Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met: // are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright // - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software. // patent holders to use this software.
// - Use of the software either in source or binary form, must be run // - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component. // on or directly connected to an Analog Devices Inc. component.
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. // PARTICULAR PURPOSE ARE DISCLAIMED.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
@ -55,6 +55,7 @@ module axi_ad9652 (
// dma interface // dma interface
adc_clk, adc_clk,
adc_rst,
adc_valid_0, adc_valid_0,
adc_enable_0, adc_enable_0,
adc_data_0, adc_data_0,
@ -111,6 +112,7 @@ module axi_ad9652 (
// dma interface // dma interface
output adc_clk; output adc_clk;
output adc_rst;
output adc_valid_0; output adc_valid_0;
output adc_enable_0; output adc_enable_0;
output [15:0] adc_data_0; output [15:0] adc_data_0;

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@ -1,44 +1 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9652_clk [get_clocks -of_objects [get_ports adc_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9652_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

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@ -19,6 +19,7 @@ adi_ip_files axi_ad9652 [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \ "$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9652_pnmon.v" \ "axi_ad9652_pnmon.v" \
"axi_ad9652_channel.v" \ "axi_ad9652_channel.v" \
"axi_ad9652_if.v" \ "axi_ad9652_if.v" \
@ -28,6 +29,7 @@ adi_ip_files axi_ad9652 [list \
adi_ip_properties axi_ad9652 adi_ip_properties axi_ad9652
adi_ip_constraints axi_ad9652 [list \ adi_ip_constraints axi_ad9652 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9652_constr.xdc" ] "axi_ad9652_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]