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axi_ad9652: Updated with the latest constraints

main
Adrian Costina 2015-09-28 11:29:07 +03:00
parent 046c89dacd
commit dff6c0df01
4 changed files with 10 additions and 48 deletions
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1
library/axi_ad9652/Makefile
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@ -22,6 +22,7 @@ M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += axi_ad9652_pnmon.v
M_DEPS += axi_ad9652_channel.v
M_DEPS += axi_ad9652_if.v

2
library/axi_ad9652/axi_ad9652.v
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@ -55,6 +55,7 @@ module axi_ad9652 (
// dma interface
adc_clk,
adc_rst,
adc_valid_0,
adc_enable_0,
adc_data_0,
@ -111,6 +112,7 @@ module axi_ad9652 (
// dma interface
output adc_clk;
output adc_rst;
output adc_valid_0;
output adc_enable_0;
output [15:0] adc_data_0;

43
library/axi_ad9652/axi_ad9652_constr.xdc
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@ -1,44 +1 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9652_clk [get_clocks -of_objects [get_ports adc_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9652_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

2
library/axi_ad9652/axi_ad9652_ip.tcl
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@ -19,6 +19,7 @@ adi_ip_files axi_ad9652 [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9652_pnmon.v" \
"axi_ad9652_channel.v" \
"axi_ad9652_if.v" \
@ -28,6 +29,7 @@ adi_ip_files axi_ad9652 [list \
adi_ip_properties axi_ad9652
adi_ip_constraints axi_ad9652 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9652_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]