axi_ad9652: Updated with the latest constraints
parent
046c89dacd
commit
dff6c0df01
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@ -22,6 +22,7 @@ M_DEPS += ../common/up_clock_mon.v
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M_DEPS += ../common/up_delay_cntrl.v
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M_DEPS += ../common/up_adc_common.v
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M_DEPS += ../common/up_adc_channel.v
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M_DEPS += ../common/ad_axi_ip_constr.xdc
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M_DEPS += axi_ad9652_pnmon.v
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M_DEPS += axi_ad9652_channel.v
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M_DEPS += axi_ad9652_if.v
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -55,6 +55,7 @@ module axi_ad9652 (
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// dma interface
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adc_clk,
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adc_rst,
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adc_valid_0,
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adc_enable_0,
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adc_data_0,
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@ -111,6 +112,7 @@ module axi_ad9652 (
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// dma interface
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output adc_clk;
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output adc_rst;
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output adc_valid_0;
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output adc_enable_0;
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output [15:0] adc_data_0;
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@ -1,44 +1 @@
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set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set ad9652_clk [get_clocks -of_objects [get_ports adc_clk]]
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set_property ASYNC_REG TRUE \
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[get_cells -hier *toggle_m1_reg*] \
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[get_cells -hier *toggle_m2_reg*] \
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[get_cells -hier *state_m1_reg*] \
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[get_cells -hier *state_m2_reg*]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $ad9652_clk]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
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@ -19,6 +19,7 @@ adi_ip_files axi_ad9652 [list \
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"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"axi_ad9652_pnmon.v" \
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"axi_ad9652_channel.v" \
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"axi_ad9652_if.v" \
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@ -28,6 +29,7 @@ adi_ip_files axi_ad9652 [list \
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adi_ip_properties axi_ad9652
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adi_ip_constraints axi_ad9652 [list \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"axi_ad9652_constr.xdc" ]
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set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
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