library/scripts: Add auto dev spec parameters
Xilinx: When calling adi_auto_fpga_spec_params in the x_ip.tcl, parameters like - FPGA_TECHNOLOGY - FPGA_FAMILY - SPEED_GRADE - DEV_PACKAGE - XCVR_TYPE - FPGA_VOLTAGE will be automatically detected and constrained to predefined pairs of values from adi_xilinx_device_info_env.tcl The parameters specified in the blobk diagram of the IP(bd.tcl), will be automatically assign when the IP is added to a block design. The "adi_auto_assign_device_spec $cellpath" is called in the init hook (bd.tcl). https://www.xilinx.com/products/technology/high-speed-serial.html Intel: Info parameters are set in the VALIDATION_CALLBACK according to adi_intel_device_info_env.tclmain
AndreiGrozav
AndreiGrozav
parent
8340d4c89d
commit
dffbbfd7d1
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@ -0,0 +1,151 @@
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## ***************************************************************************
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## ***************************************************************************
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## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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##
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## In this HDL repository, there are many different and unique modules, consisting
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## of various HDL (Verilog or VHDL) components. The individual modules are
|
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## developed independently, and may be accompanied by separate and unique license
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||||
## terms.
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||||
##
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## The user should read each of these license terms, and understand the
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## freedoms and responsibilities that he or she has by using this source/core.
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##
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## This core is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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## A PARTICULAR PURPOSE.
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##
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## Redistribution and use of source or resulting binaries, with or without modification
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## of this file, are permitted under one of the following two license terms:
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##
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## 1. The GNU General Public License version 2 as published by the
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## Free Software Foundation, which can be found in the top level directory
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## of this repository (LICENSE_GPL2), and also online at:
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## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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##
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## OR
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##
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## 2. An ADI specific BSD license, which can be found in the top level directory
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## of this repository (LICENSE_ADIBSD), and also on-line at:
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## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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## This will allow to generate bit files and not release the source code,
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## as long as it attaches to an ADI device.
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##
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## ***************************************************************************
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## ***************************************************************************
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# adi_intel_device_info_enc.tcl
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# The main rule when adding a new parameter is to have the same names for the parameter
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# and it's list (valid range type or supported entity and its encoded value type)
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variable auto_set_param_list
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variable fpga_technology_list
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variable fpga_technology
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variable fpga_family_list
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variable fpga_family
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variable speed_grade_list
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variable speed_grade
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variable dev_package_list
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variable dev_package
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variable xcvr_type_list
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variable xcvr_type
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variable fpga_voltage_list
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variable fpga_voltage
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# Parameter list for automatic assignament(generation)
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set auto_gen_param_list { \
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FPGA_TECHNOLOGY \
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FPGA_FAMILY \
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SPEED_GRADE \
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DEV_PACKAGE}
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set auto_set_param_list { \
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FPGA_VOLTAGE \
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XCVR_TYPE}
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# List for automatically assigned parameter values and encoded values
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# The list name must be the parameter name (lowercase), appending "_list" to it
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set fpga_technology_list { \
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{ Unknown 100 } \
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{ "Cyclone V" 101 } \
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{ "Cyclone 10" 102 } \
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{ "Arria 10" 103 } \
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{ "Stratix 10" 104 }}
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set fpga_family_list { \
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{ Unknown 0 } \
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{ SX 1 } \
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{ GX 2 } \
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{ GT 3 } \
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{ GZ 4 }}
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#technology 5 generation
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# family Arria SX
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set speed_grade_list { \
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{ Unknown 0 } \
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{ 1 1 } \
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{ 2 2 } \
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{ 3 3 } \
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{ 4 4 } \
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{ 5 5 } \
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{ 6 6 } \
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{ 7 7 } \
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{ 8 8 }}
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set dev_package_list { \
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{ Unknown 0 } \
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{ FBGA 1 } \
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{ UBGA 16 } \
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{ MBGA 17 }}
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# FBGA - Fine Pitch Ball Grid Array
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# FBGA - Fine Pitch Ball Grid Array
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# transceiver speedgrade
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set xcvr_type_list { 0 9 }
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set fpga_voltage_list { 0 5000 } ;# min 0mV max 5V
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################################################################################
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proc get_part_param {} {
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global fpga_technology
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global fpga_family
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global speed_grade
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global dev_package
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global xcvr_type
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global fpga_voltage
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set device [get_parameter_value DEVICE]
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# user and system values (sys_val)
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if {[catch {set fpga_technology [quartus::device::get_part_info -family $device]} fid]} {
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set fpga_technology "Unknown"
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}
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if {[catch {set fpga_family [quartus::device::get_part_info -family_variant $device]} fid]} {
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set fpga_family "Unknown"
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}
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if {[catch {set speed_grade [quartus::device::get_part_info -speed_grade $device]} fid]} {
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set speed_grade "Unknown"
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}
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if {[catch {set dev_package [quartus::device::get_part_info -package $device]} fid]} {
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set dev_package "Unknown"
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}
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if {[catch {set xcvr_type [quartus::device::get_part_info -hssi_speed_grade $device]} fid]} {
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set xcvr_type "Unknown"
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}
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if {[catch {set fpga_voltage [quartus::device::get_part_info -default_voltage $device]} fid]} {
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set fpga_voltage "0"
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}
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# user and system values (sys_val)
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regsub {V} $fpga_voltage "" fpga_voltage
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set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
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}
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## ***************************************************************************
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## ***************************************************************************
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@ -1,5 +1,8 @@
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## ###############################################################################################
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## ###############################################################################################
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source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
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## check tool version
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if {![info exists REQUIRED_VIVADO_VERSION]} {
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@ -42,10 +45,13 @@ proc adi_ip_bd {ip_name ip_bd_files} {
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if {$proj_filegroup == {}} {
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set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
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}
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set f [ipx::add_file $ip_bd_files $proj_filegroup]
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set_property -dict [list \
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type tclSource \
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] $f
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foreach file $ip_bd_files {
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set f [ipx::add_file $file $proj_filegroup]
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set_property -dict [list \
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type tclSource \
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] $f
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}
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}
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proc adi_ip_infer_streaming_interfaces {ip_name} {
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@ -304,6 +310,58 @@ proc adi_ip_properties {ip_name} {
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ipx::save_core
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}
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proc adi_add_auto_fpga_spec_params {} {
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global auto_set_param_list
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set cc [ipx::current_core]
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foreach i $auto_set_param_list {
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if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
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adi_add_device_spec_param $i
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}
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}
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}
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proc adi_add_device_spec_param {ip_param} {
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set cc [ipx::current_core]
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set list_pointer [string tolower $ip_param]
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set list_pointer [append list_pointer "_list"]
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global $list_pointer
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# set j 1D list from the original list
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foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
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# set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
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if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
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set_property -dict [list \
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"value_validation_type" "range" \
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"value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
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"value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
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[ipx::get_user_parameters $ip_param -of_objects $cc]
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} else {
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set_property -dict [list \
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"value_validation_type" "pairs" \
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"value_validation_pairs" $j ] \
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[ipx::get_user_parameters $ip_param -of_objects $cc]
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}
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# FPGA info grup
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set info_group_name "FPGA info"
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set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
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if { [string trim $info_group] eq "" } {
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set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
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set info_group [ipgui::add_group -name $info_group_name -component $cc \
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-parent $page0 -display_name $info_group_name]
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}
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set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
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set_property -dict [list "widget" "comboBox" ] $p
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ipgui::move_param -component $cc -order 0 $p -parent $info_group
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}
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## ###############################################################################################
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## ###############################################################################################
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## interface related stuff
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@ -100,7 +100,7 @@ proc ad_ip_create {pname pdisplay_name {pelabfunction ""} {pcomposefunction ""}}
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set_module_property DESCRIPTION $pdisplay_name
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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if {$pelabfunction ne ""} {
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set_module_property ELABORATION_CALLBACK $pelabfunction
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}
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@ -135,9 +135,186 @@ proc ad_ip_parameter {pname ptype pdefault {phdl true} {properties {}}} {
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###################################################################################################
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###################################################################################################
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proc adi_add_auto_fpga_spec_params {} {
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global ad_hdl_dir
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source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl
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ad_ip_parameter DEVICE STRING "" false {
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SYSTEM_INFO DEVICE
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VISIBLE false
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}
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foreach p $auto_gen_param_list {
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adi_add_device_spec_param $p
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}
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}
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###################################################################################################
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proc adi_add_device_spec_param {param} {
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global auto_gen_param_list
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global auto_set_param_list
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global fpga_technology_list
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global fpga_family_list
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global speed_grade_list
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global dev_package_list
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global xcvr_type_list
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global fpga_voltage_list
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set group "FPGA info"
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set list_pointer [string tolower $param]
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set list_pointer [append list_pointer "_list"]
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set enc_list [subst $$list_pointer]
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set ranges ""
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add_parameter $param INTEGER
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set_parameter_property $param DISPLAY_NAME $param
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set_parameter_property $param GROUP $group
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set_parameter_property $param UNITS None
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set_parameter_property $param HDL_PARAMETER true
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set_parameter_property $param VISIBLE true
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set_parameter_property $param DERIVED true
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add_parameter ${param}_MANUAL INTEGER
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set_parameter_property ${param}_MANUAL DISPLAY_NAME $param
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set_parameter_property ${param}_MANUAL GROUP $group
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set_parameter_property ${param}_MANUAL UNITS None
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set_parameter_property ${param}_MANUAL HDL_PARAMETER false
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set_parameter_property ${param}_MANUAL VISIBLE false
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set_parameter_property ${param}_MANUAL DEFAULT_VALUE [lindex $enc_list 0 1]
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foreach i $enc_list {
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set value [lindex $i 0]
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set encode [lindex $i 1]
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append ranges "\"$encode\:$value\" "
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}
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set_parameter_property $param ALLOWED_RANGES $ranges
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set_parameter_property ${param}_MANUAL ALLOWED_RANGES $ranges
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}
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###################################################################################################
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proc adi_add_indep_spec_params_overwrite {param} {
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add_parameter ${param}_USER_OVERWRITE BOOLEAN 0
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set_parameter_property ${param}_USER_OVERWRITE DISPLAY_NAME "Manually overwrite $param parameter"
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set_parameter_property ${param}_USER_OVERWRITE HDL_PARAMETER false
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set_parameter_property ${param}_USER_OVERWRITE GROUP {FPGA info}
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}
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###################################################################################################
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proc info_param_validate {} {
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global ad_hdl_dir
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global fpga_technology
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global fpga_family
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global speed_grade
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global dev_package
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global xcvr_type
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global fpga_voltage
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source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl
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set device [get_parameter_value DEVICE]
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set auto_populate true ;# for future code dev
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set all_ip_param_list [get_parameters]
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set validate_list ""
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set independent_overwrite_list ""
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foreach param $all_ip_param_list {
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foreach elem [concat $auto_gen_param_list $auto_set_param_list] {
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if { "$elem" == "$param" } {
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append validate_list "$param "
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}
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if { [regexp ${elem}_USER_OVERWRITE $param] } {
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append independent_overwrite_list "$elem "
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}
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}
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}
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set indep_overwrite [expr {[llength $independent_overwrite_list] != 0} ? 1 : 0]
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if { $auto_populate == true } {
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get_part_param ;# in adi_intel_device_info_enc.tcl
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# point parameters and assign
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foreach param $validate_list {
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set ls_param [string tolower $param]
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set list_pointer $ls_param
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append list_pointer "_list"
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set pointer_to_sys_val [subst $$ls_param] ;# e.g., $fpga_technology
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set enc_list_pointer [subst $$list_pointer] ;# e.g., $fpga_technology_list
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# get_part_info returns '{'#value'}'
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regsub -all "{" $pointer_to_sys_val "" pointer_to_sys_val
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regsub -all "}" $pointer_to_sys_val "" pointer_to_sys_val
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# the list defines a range or pairs of values
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set get_list_correspondence 1
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if { [llength $enc_list_pointer] != 0 } {
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if { [llength $enc_list_pointer] == 2 } {
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if { [llength [lindex $enc_list_pointer 0]] == 1 } {
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set get_list_correspondence 0
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}
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}
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} else {
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send_message ERROR "No list $list_pointer defined in adi_intel_device_info_enc.tcl for parameter $param"
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}
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# auto assign parameter value
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if { $get_list_correspondence } {
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set matched ""
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foreach i $enc_list_pointer {
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if { [regexp ^[lindex $i 0] $pointer_to_sys_val] } {
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set matched [lindex $i 1]
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}
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}
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if { $matched == "" } {
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send_message ERROR "Unknown or undefined(adi_intel_device_info_enc.tcl) $param \"$pointer_to_sys_val\" form \"$device\" device"
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} else {
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set_parameter_value $param $matched
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}
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} else {
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set_parameter_value $param $pointer_to_sys_val
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}
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}
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} else {
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foreach p $validate_list {
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set_parameter_value $p [get_parameter_value ${p}_MANUAL]
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}
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}
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# display manual(writable) or auto(non-writable) parametes
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foreach p $validate_list {
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set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_populate ? false : true]
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set_parameter_property $p VISIBLE $auto_populate
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if { $indep_overwrite == 1 } {
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foreach p_overwrite $independent_overwrite_list {
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if { $p == $p_overwrite } {
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set p_over_val [get_parameter_value ${p}_USER_OVERWRITE]
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# set the hdl parameter with the independent manual overwritten value
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if { $p_over_val } {
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set_parameter_value $p [get_parameter_value ${p}_MANUAL]
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set_parameter_property ${p}_MANUAL VISIBLE $p_over_val
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set_parameter_property $p VISIBLE [expr $p_over_val ? false : true]
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}
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}
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}
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}
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_ip_addfile {pname pfile} {
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set pmodule [file tail $pfile]
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set pmodule [file tail $pfile]
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regsub {\..$} $pmodule {} mname
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if {$pname eq $mname} {
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|
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@ -0,0 +1,191 @@
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## ***************************************************************************
|
||||
## ***************************************************************************
|
||||
## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
##
|
||||
## In this HDL repository, there are many different and unique modules, consisting
|
||||
## of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
## developed independently, and may be accompanied by separate and unique license
|
||||
## terms.
|
||||
##
|
||||
## The user should read each of these license terms, and understand the
|
||||
## freedoms and responsibilities that he or she has by using this source/core.
|
||||
##
|
||||
## This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
## A PARTICULAR PURPOSE.
|
||||
##
|
||||
## Redistribution and use of source or resulting binaries, with or without modification
|
||||
## of this file, are permitted under one of the following two license terms:
|
||||
##
|
||||
## 1. The GNU General Public License version 2 as published by the
|
||||
## Free Software Foundation, which can be found in the top level directory
|
||||
## of this repository (LICENSE_GPL2), and also online at:
|
||||
## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
##
|
||||
## OR
|
||||
##
|
||||
## 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
## of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
## This will allow to generate bit files and not release the source code,
|
||||
## as long as it attaches to an ADI device.
|
||||
##
|
||||
## ***************************************************************************
|
||||
## ***************************************************************************
|
||||
|
||||
# adi_xilinx_device_info_enc.tcl
|
||||
|
||||
variable auto_set_param_list
|
||||
variable fpga_series_list
|
||||
variable fpga_family_list
|
||||
variable speed_grade_list
|
||||
variable dev_package_list
|
||||
variable xcvr_type_list
|
||||
variable fpga_voltage_list
|
||||
|
||||
# Parameter list for automatic assignament
|
||||
set auto_set_param_list {
|
||||
FPGA_VOLTAGE \
|
||||
XCVR_TYPE \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY}
|
||||
|
||||
|
||||
# List for automatically assigned parameter values and encoded values
|
||||
# The list name must be the parameter name (lowercase), appending "_list" to it
|
||||
set fpga_technology_list { \
|
||||
{ Unknown 0 } \
|
||||
{ 7series 1 } \
|
||||
{ ultrascale 2 } \
|
||||
{ ultrascale+ 3 }}
|
||||
|
||||
set fpga_family_list { \
|
||||
{ Unknown 0 } \
|
||||
{ artix 1 } \
|
||||
{ kintex 2 } \
|
||||
{ virtex 3 } \
|
||||
{ zynq 4 }}
|
||||
|
||||
set speed_grade_list { \
|
||||
{ Unknown 0 } \
|
||||
{ -1 10 } \
|
||||
{ -1L 11 } \
|
||||
{ -1H 12 } \
|
||||
{ -1HV 13 } \
|
||||
{ -1LV 14 } \
|
||||
{ -2 20 } \
|
||||
{ -2L 21 } \
|
||||
{ -2LV 22 } \
|
||||
{ -3 30 }}
|
||||
|
||||
set dev_package_list { \
|
||||
{ Unknown 0 } \
|
||||
{ rf 1 } \
|
||||
{ fl 2 } \
|
||||
{ ff 3 } \
|
||||
{ fb 4 } \
|
||||
{ hc 5 } \
|
||||
{ fh 6 } \
|
||||
{ cs 7 } \
|
||||
{ cp 8 } \
|
||||
{ ft 9 } \
|
||||
{ fg 10 } \
|
||||
{ sb 11 } \
|
||||
{ rb 12 } \
|
||||
{ rs 13 } \
|
||||
{ cl 14 } \
|
||||
{ sf 15 } \
|
||||
{ ba 16 } \
|
||||
{ fa 17 }}
|
||||
|
||||
set xcvr_type_list { \
|
||||
{ Unknown 0 } \
|
||||
{ GTPE2_NOT_SUPPORTED 1 } \
|
||||
{ GTXE2 2 } \
|
||||
{ GTHE2_NOT_SUPPORTED 3 } \
|
||||
{ GTZE2_NOT_SUPPORTED 4 } \
|
||||
{ GTHE3 5 } \
|
||||
{ GTYE3_NOT_SUPPORTED 6 } \
|
||||
{ GTRE4_NOT_SUPPORTED 7 } \
|
||||
{ GTHE4 8 } \
|
||||
{ GTYE4_NOT_SUPPORTED 9 } \
|
||||
{ GTME4_NOT_SUPPORTED 10}}
|
||||
|
||||
set fpga_voltage_list {0 5000} ;# 0 to 5000mV
|
||||
|
||||
|
||||
## ***************************************************************************
|
||||
|
||||
proc adi_device_spec {cellpath param} {
|
||||
|
||||
set list_pointer [string tolower $param]
|
||||
set list_pointer [append list_pointer "_list"]
|
||||
|
||||
upvar 1 $list_pointer $list_pointer
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set part [get_property PART [current_project]]
|
||||
|
||||
switch -regexp -- $param {
|
||||
FPGA_TECHNOLOGY {
|
||||
switch -regexp -- $part {
|
||||
^xc7 {set series_name 7series}
|
||||
^xczu {set series_name ultrascale+}
|
||||
^xc.u.p {set series_name ultrascale+}
|
||||
^xc.u {set series_name ultrascale }
|
||||
default {
|
||||
puts "Undefined fpga technology for \"$part\"!"
|
||||
exit -1
|
||||
}
|
||||
}
|
||||
return "$series_name"
|
||||
}
|
||||
FPGA_FAMILY {
|
||||
set fpga_family [get_property FAMILY $part]
|
||||
foreach i $fpga_family_list {
|
||||
regexp ^[lindex $i 0] $fpga_family matched
|
||||
}
|
||||
return "$matched"
|
||||
}
|
||||
SPEED_GRADE {
|
||||
set speed_grade [get_property SPEED $part]
|
||||
return "$speed_grade"
|
||||
}
|
||||
DEV_PACKAGE {
|
||||
set dev_package [get_property PACKAGE $part]
|
||||
foreach i $dev_package_list {
|
||||
regexp ^[lindex $i 0] $dev_package matched
|
||||
}
|
||||
return "$matched"
|
||||
}
|
||||
XCVR_TYPE {
|
||||
set matched ""
|
||||
set dev_transcivers "none"
|
||||
foreach x [list_property $part] {
|
||||
regexp ^GT..._TRANSCEIVERS $x dev_transcivers
|
||||
}
|
||||
foreach i $xcvr_type_list {
|
||||
regexp ^[lindex $i 0] $dev_transcivers matched
|
||||
}
|
||||
if { $matched eq "" } {
|
||||
puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
|
||||
}
|
||||
return "$matched"
|
||||
}
|
||||
FPGA_VOLTAGE {
|
||||
set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
|
||||
set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
|
||||
|
||||
return "$fpga_voltage"
|
||||
}
|
||||
default {
|
||||
puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
## ***************************************************************************
|
||||
## ***************************************************************************
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
################################################################################
|
||||
################################################################################
|
||||
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue