diff --git a/library/scripts/adi_intel_device_info_enc.tcl b/library/scripts/adi_intel_device_info_enc.tcl new file mode 100644 index 000000000..0e660ce5b --- /dev/null +++ b/library/scripts/adi_intel_device_info_enc.tcl @@ -0,0 +1,151 @@ +## *************************************************************************** +## *************************************************************************** +## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +## +## In this HDL repository, there are many different and unique modules, consisting +## of various HDL (Verilog or VHDL) components. The individual modules are +## developed independently, and may be accompanied by separate and unique license +## terms. +## +## The user should read each of these license terms, and understand the +## freedoms and responsibilities that he or she has by using this source/core. +## +## This core is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +## A PARTICULAR PURPOSE. +## +## Redistribution and use of source or resulting binaries, with or without modification +## of this file, are permitted under one of the following two license terms: +## +## 1. The GNU General Public License version 2 as published by the +## Free Software Foundation, which can be found in the top level directory +## of this repository (LICENSE_GPL2), and also online at: +## +## +## OR +## +## 2. An ADI specific BSD license, which can be found in the top level directory +## of this repository (LICENSE_ADIBSD), and also on-line at: +## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +## This will allow to generate bit files and not release the source code, +## as long as it attaches to an ADI device. +## +## *************************************************************************** +## *************************************************************************** + +# adi_intel_device_info_enc.tcl + +# The main rule when adding a new parameter is to have the same names for the parameter +# and it's list (valid range type or supported entity and its encoded value type) + +variable auto_set_param_list +variable fpga_technology_list +variable fpga_technology +variable fpga_family_list +variable fpga_family +variable speed_grade_list +variable speed_grade +variable dev_package_list +variable dev_package +variable xcvr_type_list +variable xcvr_type +variable fpga_voltage_list +variable fpga_voltage + +# Parameter list for automatic assignament(generation) +set auto_gen_param_list { \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE} + +set auto_set_param_list { \ + FPGA_VOLTAGE \ + XCVR_TYPE} + + +# List for automatically assigned parameter values and encoded values +# The list name must be the parameter name (lowercase), appending "_list" to it +set fpga_technology_list { \ + { Unknown 100 } \ + { "Cyclone V" 101 } \ + { "Cyclone 10" 102 } \ + { "Arria 10" 103 } \ + { "Stratix 10" 104 }} + +set fpga_family_list { \ + { Unknown 0 } \ + { SX 1 } \ + { GX 2 } \ + { GT 3 } \ + { GZ 4 }} + + #technology 5 generation + # family Arria SX + +set speed_grade_list { \ + { Unknown 0 } \ + { 1 1 } \ + { 2 2 } \ + { 3 3 } \ + { 4 4 } \ + { 5 5 } \ + { 6 6 } \ + { 7 7 } \ + { 8 8 }} + +set dev_package_list { \ + { Unknown 0 } \ + { FBGA 1 } \ + { UBGA 16 } \ + { MBGA 17 }} + +# FBGA - Fine Pitch Ball Grid Array +# FBGA - Fine Pitch Ball Grid Array + +# transceiver speedgrade +set xcvr_type_list { 0 9 } + +set fpga_voltage_list { 0 5000 } ;# min 0mV max 5V + +################################################################################ + +proc get_part_param {} { + + global fpga_technology + global fpga_family + global speed_grade + global dev_package + global xcvr_type + global fpga_voltage + + set device [get_parameter_value DEVICE] + + # user and system values (sys_val) + if {[catch {set fpga_technology [quartus::device::get_part_info -family $device]} fid]} { + set fpga_technology "Unknown" + } + if {[catch {set fpga_family [quartus::device::get_part_info -family_variant $device]} fid]} { + set fpga_family "Unknown" + } + if {[catch {set speed_grade [quartus::device::get_part_info -speed_grade $device]} fid]} { + set speed_grade "Unknown" + } + if {[catch {set dev_package [quartus::device::get_part_info -package $device]} fid]} { + set dev_package "Unknown" + } + if {[catch {set xcvr_type [quartus::device::get_part_info -hssi_speed_grade $device]} fid]} { + set xcvr_type "Unknown" + } + if {[catch {set fpga_voltage [quartus::device::get_part_info -default_voltage $device]} fid]} { + set fpga_voltage "0" + } + + # user and system values (sys_val) + regsub {V} $fpga_voltage "" fpga_voltage + set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) + +} + +## *************************************************************************** +## *************************************************************************** diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index df83cc579..d5dd719ae 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -1,5 +1,8 @@ ## ############################################################################################### ## ############################################################################################### + +source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl + ## check tool version if {![info exists REQUIRED_VIVADO_VERSION]} { @@ -42,10 +45,13 @@ proc adi_ip_bd {ip_name ip_bd_files} { if {$proj_filegroup == {}} { set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] } - set f [ipx::add_file $ip_bd_files $proj_filegroup] - set_property -dict [list \ - type tclSource \ - ] $f + + foreach file $ip_bd_files { + set f [ipx::add_file $file $proj_filegroup] + set_property -dict [list \ + type tclSource \ + ] $f + } } proc adi_ip_infer_streaming_interfaces {ip_name} { @@ -304,6 +310,58 @@ proc adi_ip_properties {ip_name} { ipx::save_core } +proc adi_add_auto_fpga_spec_params {} { + + global auto_set_param_list + set cc [ipx::current_core] + + foreach i $auto_set_param_list { + if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { + adi_add_device_spec_param $i + } + } +} + +proc adi_add_device_spec_param {ip_param} { + + set cc [ipx::current_core] + + set list_pointer [string tolower $ip_param] + set list_pointer [append list_pointer "_list"] + + global $list_pointer + + # set j 1D list from the original list + foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} + + # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) + if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { + set_property -dict [list \ + "value_validation_type" "range" \ + "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ + "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ + [ipx::get_user_parameters $ip_param -of_objects $cc] + } else { + set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" $j ] \ + [ipx::get_user_parameters $ip_param -of_objects $cc] + } + + # FPGA info grup + set info_group_name "FPGA info" + set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] + if { [string trim $info_group] eq "" } { + set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + set info_group [ipgui::add_group -name $info_group_name -component $cc \ + -parent $page0 -display_name $info_group_name] + } + + set p [ipgui::get_guiparamspec -name $ip_param -component $cc] + set_property -dict [list "widget" "comboBox" ] $p + ipgui::move_param -component $cc -order 0 $p -parent $info_group +} + ## ############################################################################################### ## ############################################################################################### ## interface related stuff diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl index ffd08d3ee..12c77007c 100644 --- a/library/scripts/adi_ip_alt.tcl +++ b/library/scripts/adi_ip_alt.tcl @@ -100,7 +100,7 @@ proc ad_ip_create {pname pdisplay_name {pelabfunction ""} {pcomposefunction ""}} set_module_property DESCRIPTION $pdisplay_name set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" - + if {$pelabfunction ne ""} { set_module_property ELABORATION_CALLBACK $pelabfunction } @@ -135,9 +135,186 @@ proc ad_ip_parameter {pname ptype pdefault {phdl true} {properties {}}} { ################################################################################################### ################################################################################################### +proc adi_add_auto_fpga_spec_params {} { + + global ad_hdl_dir + source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl + + ad_ip_parameter DEVICE STRING "" false { + SYSTEM_INFO DEVICE + VISIBLE false + } + + foreach p $auto_gen_param_list { + adi_add_device_spec_param $p + } +} + +################################################################################################### + +proc adi_add_device_spec_param {param} { + + global auto_gen_param_list + global auto_set_param_list + global fpga_technology_list + global fpga_family_list + global speed_grade_list + global dev_package_list + global xcvr_type_list + global fpga_voltage_list + + set group "FPGA info" + + set list_pointer [string tolower $param] + set list_pointer [append list_pointer "_list"] + + set enc_list [subst $$list_pointer] + + set ranges "" + + add_parameter $param INTEGER + set_parameter_property $param DISPLAY_NAME $param + set_parameter_property $param GROUP $group + set_parameter_property $param UNITS None + set_parameter_property $param HDL_PARAMETER true + set_parameter_property $param VISIBLE true + set_parameter_property $param DERIVED true + + add_parameter ${param}_MANUAL INTEGER + set_parameter_property ${param}_MANUAL DISPLAY_NAME $param + set_parameter_property ${param}_MANUAL GROUP $group + set_parameter_property ${param}_MANUAL UNITS None + set_parameter_property ${param}_MANUAL HDL_PARAMETER false + set_parameter_property ${param}_MANUAL VISIBLE false + set_parameter_property ${param}_MANUAL DEFAULT_VALUE [lindex $enc_list 0 1] + + foreach i $enc_list { + set value [lindex $i 0] + set encode [lindex $i 1] + append ranges "\"$encode\:$value\" " + } + set_parameter_property $param ALLOWED_RANGES $ranges + set_parameter_property ${param}_MANUAL ALLOWED_RANGES $ranges +} + +################################################################################################### + +proc adi_add_indep_spec_params_overwrite {param} { + add_parameter ${param}_USER_OVERWRITE BOOLEAN 0 + set_parameter_property ${param}_USER_OVERWRITE DISPLAY_NAME "Manually overwrite $param parameter" + set_parameter_property ${param}_USER_OVERWRITE HDL_PARAMETER false + set_parameter_property ${param}_USER_OVERWRITE GROUP {FPGA info} +} + +################################################################################################### + +proc info_param_validate {} { + global ad_hdl_dir + global fpga_technology + global fpga_family + global speed_grade + global dev_package + global xcvr_type + global fpga_voltage + + source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl + + set device [get_parameter_value DEVICE] + set auto_populate true ;# for future code dev + + set all_ip_param_list [get_parameters] + set validate_list "" + set independent_overwrite_list "" + foreach param $all_ip_param_list { + foreach elem [concat $auto_gen_param_list $auto_set_param_list] { + if { "$elem" == "$param" } { + append validate_list "$param " + } + if { [regexp ${elem}_USER_OVERWRITE $param] } { + append independent_overwrite_list "$elem " + } + } + } + + set indep_overwrite [expr {[llength $independent_overwrite_list] != 0} ? 1 : 0] + + if { $auto_populate == true } { + + get_part_param ;# in adi_intel_device_info_enc.tcl + + # point parameters and assign + foreach param $validate_list { + set ls_param [string tolower $param] + set list_pointer $ls_param + append list_pointer "_list" + set pointer_to_sys_val [subst $$ls_param] ;# e.g., $fpga_technology + set enc_list_pointer [subst $$list_pointer] ;# e.g., $fpga_technology_list + + # get_part_info returns '{'#value'}' + regsub -all "{" $pointer_to_sys_val "" pointer_to_sys_val + regsub -all "}" $pointer_to_sys_val "" pointer_to_sys_val + + # the list defines a range or pairs of values + set get_list_correspondence 1 + if { [llength $enc_list_pointer] != 0 } { + if { [llength $enc_list_pointer] == 2 } { + if { [llength [lindex $enc_list_pointer 0]] == 1 } { + set get_list_correspondence 0 + } + } + } else { + send_message ERROR "No list $list_pointer defined in adi_intel_device_info_enc.tcl for parameter $param" + } + + # auto assign parameter value + if { $get_list_correspondence } { + set matched "" + foreach i $enc_list_pointer { + if { [regexp ^[lindex $i 0] $pointer_to_sys_val] } { + set matched [lindex $i 1] + } + } + if { $matched == "" } { + send_message ERROR "Unknown or undefined(adi_intel_device_info_enc.tcl) $param \"$pointer_to_sys_val\" form \"$device\" device" + } else { + set_parameter_value $param $matched + } + } else { + set_parameter_value $param $pointer_to_sys_val + } + } + } else { + foreach p $validate_list { + set_parameter_value $p [get_parameter_value ${p}_MANUAL] + } + } + + # display manual(writable) or auto(non-writable) parametes + foreach p $validate_list { + set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_populate ? false : true] + set_parameter_property $p VISIBLE $auto_populate + if { $indep_overwrite == 1 } { + foreach p_overwrite $independent_overwrite_list { + if { $p == $p_overwrite } { + set p_over_val [get_parameter_value ${p}_USER_OVERWRITE] + # set the hdl parameter with the independent manual overwritten value + if { $p_over_val } { + set_parameter_value $p [get_parameter_value ${p}_MANUAL] + set_parameter_property ${p}_MANUAL VISIBLE $p_over_val + set_parameter_property $p VISIBLE [expr $p_over_val ? false : true] + } + } + } + } + } +} + +################################################################################################### +################################################################################################### + proc ad_ip_addfile {pname pfile} { - set pmodule [file tail $pfile] + set pmodule [file tail $pfile] regsub {\..$} $pmodule {} mname if {$pname eq $mname} { diff --git a/library/scripts/adi_xilinx_device_info_enc.tcl b/library/scripts/adi_xilinx_device_info_enc.tcl new file mode 100644 index 000000000..8115a39b7 --- /dev/null +++ b/library/scripts/adi_xilinx_device_info_enc.tcl @@ -0,0 +1,191 @@ +## *************************************************************************** +## *************************************************************************** +## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +## +## In this HDL repository, there are many different and unique modules, consisting +## of various HDL (Verilog or VHDL) components. The individual modules are +## developed independently, and may be accompanied by separate and unique license +## terms. +## +## The user should read each of these license terms, and understand the +## freedoms and responsibilities that he or she has by using this source/core. +## +## This core is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +## A PARTICULAR PURPOSE. +## +## Redistribution and use of source or resulting binaries, with or without modification +## of this file, are permitted under one of the following two license terms: +## +## 1. The GNU General Public License version 2 as published by the +## Free Software Foundation, which can be found in the top level directory +## of this repository (LICENSE_GPL2), and also online at: +## +## +## OR +## +## 2. An ADI specific BSD license, which can be found in the top level directory +## of this repository (LICENSE_ADIBSD), and also on-line at: +## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +## This will allow to generate bit files and not release the source code, +## as long as it attaches to an ADI device. +## +## *************************************************************************** +## *************************************************************************** + +# adi_xilinx_device_info_enc.tcl + +variable auto_set_param_list +variable fpga_series_list +variable fpga_family_list +variable speed_grade_list +variable dev_package_list +variable xcvr_type_list +variable fpga_voltage_list + +# Parameter list for automatic assignament +set auto_set_param_list { + FPGA_VOLTAGE \ + XCVR_TYPE \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY} + + +# List for automatically assigned parameter values and encoded values +# The list name must be the parameter name (lowercase), appending "_list" to it +set fpga_technology_list { \ + { Unknown 0 } \ + { 7series 1 } \ + { ultrascale 2 } \ + { ultrascale+ 3 }} + +set fpga_family_list { \ + { Unknown 0 } \ + { artix 1 } \ + { kintex 2 } \ + { virtex 3 } \ + { zynq 4 }} + +set speed_grade_list { \ + { Unknown 0 } \ + { -1 10 } \ + { -1L 11 } \ + { -1H 12 } \ + { -1HV 13 } \ + { -1LV 14 } \ + { -2 20 } \ + { -2L 21 } \ + { -2LV 22 } \ + { -3 30 }} + +set dev_package_list { \ + { Unknown 0 } \ + { rf 1 } \ + { fl 2 } \ + { ff 3 } \ + { fb 4 } \ + { hc 5 } \ + { fh 6 } \ + { cs 7 } \ + { cp 8 } \ + { ft 9 } \ + { fg 10 } \ + { sb 11 } \ + { rb 12 } \ + { rs 13 } \ + { cl 14 } \ + { sf 15 } \ + { ba 16 } \ + { fa 17 }} + +set xcvr_type_list { \ + { Unknown 0 } \ + { GTPE2_NOT_SUPPORTED 1 } \ + { GTXE2 2 } \ + { GTHE2_NOT_SUPPORTED 3 } \ + { GTZE2_NOT_SUPPORTED 4 } \ + { GTHE3 5 } \ + { GTYE3_NOT_SUPPORTED 6 } \ + { GTRE4_NOT_SUPPORTED 7 } \ + { GTHE4 8 } \ + { GTYE4_NOT_SUPPORTED 9 } \ + { GTME4_NOT_SUPPORTED 10}} + +set fpga_voltage_list {0 5000} ;# 0 to 5000mV + + +## *************************************************************************** + +proc adi_device_spec {cellpath param} { + + set list_pointer [string tolower $param] + set list_pointer [append list_pointer "_list"] + + upvar 1 $list_pointer $list_pointer + + set ip [get_bd_cells $cellpath] + set part [get_property PART [current_project]] + + switch -regexp -- $param { + FPGA_TECHNOLOGY { + switch -regexp -- $part { + ^xc7 {set series_name 7series} + ^xczu {set series_name ultrascale+} + ^xc.u.p {set series_name ultrascale+} + ^xc.u {set series_name ultrascale } + default { + puts "Undefined fpga technology for \"$part\"!" + exit -1 + } + } + return "$series_name" + } + FPGA_FAMILY { + set fpga_family [get_property FAMILY $part] + foreach i $fpga_family_list { + regexp ^[lindex $i 0] $fpga_family matched + } + return "$matched" + } + SPEED_GRADE { + set speed_grade [get_property SPEED $part] + return "$speed_grade" + } + DEV_PACKAGE { + set dev_package [get_property PACKAGE $part] + foreach i $dev_package_list { + regexp ^[lindex $i 0] $dev_package matched + } + return "$matched" + } + XCVR_TYPE { + set matched "" + set dev_transcivers "none" + foreach x [list_property $part] { + regexp ^GT..._TRANSCEIVERS $x dev_transcivers + } + foreach i $xcvr_type_list { + regexp ^[lindex $i 0] $dev_transcivers matched + } + if { $matched eq "" } { + puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" + } + return "$matched" + } + FPGA_VOLTAGE { + set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] + set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) + + return "$fpga_voltage" + } + default { + puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" + } + } +} + + +## *************************************************************************** +## *************************************************************************** diff --git a/library/scripts/common_bd.tcl b/library/scripts/common_bd.tcl new file mode 100644 index 000000000..96e28d463 --- /dev/null +++ b/library/scripts/common_bd.tcl @@ -0,0 +1,29 @@ +################################################################################ +################################################################################ + + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +}