ad9081_fmca_ebz: versal: Remove external gt_reset logic

main
Laszlo Nagy 2021-11-12 11:04:25 +00:00 committed by Laszlo Nagy
parent 0b9631f1f7
commit e00def31d0
2 changed files with 1 additions and 15 deletions

View File

@ -137,8 +137,6 @@ if {$ADI_PHY_SEL == 1} {
create_versal_phy jesd204_phy $TX_NUM_OF_LANES
create_bd_port -dir I gt_reset
}
if {$ADI_PHY_SEL == 1} {
@ -306,8 +304,6 @@ if {$ADI_PHY_SEL == 1} {
ad_connect $sys_cpu_clk jesd204_phy/apb3clk
ad_connect gt_reset jesd204_phy/gtreset_in
ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_pll_and_datapath_in
ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_pll_and_datapath_in

View File

@ -225,15 +225,6 @@ module system_top #(
assign gpio_i[94:54] = gpio_o[94:54];
assign gpio_i[31:10] = gpio_o[31:10];
reg ext_pll_lock,ext_pll_lock_d;
always @(posedge tx_device_clk) begin
ext_pll_lock <= gpio_i[43];
ext_pll_lock_d <= ext_pll_lock;
end
assign gt_reset = ext_pll_lock & ~ext_pll_lock_d;
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
@ -283,8 +274,7 @@ module system_top #(
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref),
.gt_reset (gt_reset)
.tx_sysref_0 (sysref)
);
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];