From 89f7aadfb1306ebb3180971e2d8b0800cc1813ff Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 23 Feb 2016 11:31:07 +0200 Subject: [PATCH 1/3] fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output This will allow for the transceivers to be reset by the axi_jesd_xcvr core --- projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys index c3abb1886..780a3c68b 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys @@ -631,8 +631,8 @@ - - + + @@ -1228,6 +1228,11 @@ version="15.1" start="axi_jesd_xcvr.if_rst" end="xcvr_rx_pll.reset" /> + - Date: Tue, 23 Feb 2016 11:41:38 +0200 Subject: [PATCH 2/3] daq2: A10GX, increase analog/digital reset durations - reset the xcvr_rst_cntrl only from the axi_jesd_xcvr - checked separate RX/TX reset per channel --- projects/daq2/common/daq2_bd.qsys | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys index 6ead3df40..0f76e66a9 100755 --- a/projects/daq2/common/daq2_bd.qsys +++ b/projects/daq2/common/daq2_bd.qsys @@ -978,19 +978,19 @@ - + - + - - + + @@ -2220,11 +2220,6 @@ version="15.1" start="mem_rst.out_reset" end="axi_ad9144_dma.m_src_axi_reset" /> - Date: Fri, 26 Feb 2016 13:19:49 -0500 Subject: [PATCH 3/3] kcu105: add ethernet idelaycntrl --- projects/common/kcu105/kcu105_system_bd.tcl | 4 ++++ projects/common/kcu105/kcu105_system_constr.xdc | 2 ++ 2 files changed, 6 insertions(+) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 18afaddc7..512058517 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -100,6 +100,7 @@ set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen] +set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl] set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet] set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet @@ -234,6 +235,9 @@ ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n +ad_connect axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in +ad_connect axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset +ad_connect axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3 # defaults (misc) diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc index d32fa63a0..fb6306582 100644 --- a/projects/common/kcu105/kcu105_system_constr.xdc +++ b/projects/common/kcu105/kcu105_system_constr.xdc @@ -176,3 +176,5 @@ set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46] +set_false_path -to [get_pins -hier -filter {name =~ *axi_ethernet_idelayctrl*/RST}] +