Merge remote-tracking branch 'origin/hdl_2015_r2' into dev

main
Rejeesh Kutty 2016-02-26 13:39:39 -05:00
commit e012d0519b
4 changed files with 17 additions and 16 deletions

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@ -100,6 +100,7 @@ set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen
set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen
set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen]
set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl]
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
@ -234,6 +235,9 @@ ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n
ad_connect axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in
ad_connect axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset
ad_connect axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3
# defaults (misc)

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@ -176,3 +176,5 @@ set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44]
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45]
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46]
set_false_path -to [get_pins -hier -filter {name =~ *axi_ethernet_idelayctrl*/RST}]

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@ -978,19 +978,19 @@
<parameter name="PLLS" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
<parameter name="RX_ENABLE" value="1" />
<parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="RX_PER_CHANNEL" value="1" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
<parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="100" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
<parameter name="TX_PER_CHANNEL" value="1" />
<parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="0" />
<parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="T_TX_ANALOGRESET" value="40" />
<parameter name="T_TX_DIGITALRESET" value="4000" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="1" />
<parameter name="gui_rx_auto_reset" value="0" />
@ -2220,11 +2220,6 @@
version="15.1"
start="mem_rst.out_reset"
end="axi_ad9144_dma.m_src_axi_reset" />
<connection
kind="reset"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.1"

View File

@ -631,8 +631,8 @@
<parameter name="TX_PLL_ENABLE" value="0" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="80" />
<parameter name="T_RX_DIGITALRESET" value="8000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="0" />
<parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="device_family" value="Arria V" />
@ -1228,6 +1228,11 @@
version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rx_pll.reset" />
<connection
kind="reset"
version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.1"
@ -1248,11 +1253,6 @@
version="15.1"
start="mem_rst.out_reset"
end="axi_dmac_0.m_dest_axi_reset" />
<connection
kind="reset"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.1"