diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl
index ac3220625..b1c13770d 100755
--- a/library/axi_ad9144/axi_ad9144_hw.tcl
+++ b/library/axi_ad9144/axi_ad9144_hw.tcl
@@ -14,7 +14,7 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
 add_fileset_file ad_mul.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
 add_fileset_file ad_dds_sine.v        VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl
index 56c930dff..62e950133 100755
--- a/library/axi_ad9250/axi_ad9250_hw.tcl
+++ b/library/axi_ad9250/axi_ad9250_hw.tcl
@@ -12,7 +12,7 @@ set_module_property DISPLAY_NAME axi_ad9250
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_pnmon.v           VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_datafmt.v         VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
 add_fileset_file up_axi.v             VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 43e24e384..f3374e13e 100755
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -12,7 +12,7 @@ set_module_property DISPLAY_NAME axi_ad9361
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
-add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
+add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v
 add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v
 add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v
diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl
index 42b162020..05307cefa 100644
--- a/library/axi_ad9671/axi_ad9671_hw.tcl
+++ b/library/axi_ad9671/axi_ad9671_hw.tcl
@@ -12,7 +12,7 @@ set_module_property DISPLAY_NAME axi_ad9671
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9671
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_pnmon.v           VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_datafmt.v         VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
 add_fileset_file up_axi.v             VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl
index bfa652d07..1f10569a9 100755
--- a/library/axi_ad9680/axi_ad9680_hw.tcl
+++ b/library/axi_ad9680/axi_ad9680_hw.tcl
@@ -13,7 +13,7 @@ set_module_property DISPLAY_NAME axi_ad9680
 
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9680
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_pnmon.v           VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_datafmt.v         VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
 add_fileset_file up_axi.v             VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
index ce1049dbb..bc0abe6fd 100755
--- a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
@@ -13,7 +13,7 @@ set_module_property DISPLAY_NAME axi_hdmi_tx
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_hdmi_tx_alt
 add_fileset_file MULT_MACRO.v         VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
-add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
+add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
 add_fileset_file ad_mem.v             VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
 add_fileset_file ad_csc_1_mul.v       VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_mul.v
 add_fileset_file ad_csc_1_add.v       VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_add.v