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ad_rst- non lpm version

main
Rejeesh Kutty 2015-06-04 10:49:17 -04:00
parent 264dbfed35
commit e02273781f
6 changed files with 6 additions and 6 deletions
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2
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -14,7 +14,7 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9144 set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v

2
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -12,7 +12,7 @@ set_module_property DISPLAY_NAME axi_ad9250
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v

2
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -12,7 +12,7 @@ set_module_property DISPLAY_NAME axi_ad9361
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9361 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_lvds_clk.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v add_fileset_file ad_lvds_clk.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v
add_fileset_file ad_lvds_in.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v add_fileset_file ad_lvds_in.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v
add_fileset_file ad_lvds_out.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v add_fileset_file ad_lvds_out.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v

2
library/axi_ad9671/axi_ad9671_hw.tcl
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@ -12,7 +12,7 @@ set_module_property DISPLAY_NAME axi_ad9671
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9671 set_fileset_property quartus_synth TOP_LEVEL axi_ad9671
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v

2
library/axi_ad9680/axi_ad9680_hw.tcl
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@ -13,7 +13,7 @@ set_module_property DISPLAY_NAME axi_ad9680
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9680 set_fileset_property quartus_synth TOP_LEVEL axi_ad9680
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v

2
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
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@ -13,7 +13,7 @@ set_module_property DISPLAY_NAME axi_hdmi_tx
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_hdmi_tx_alt set_fileset_property quartus_synth TOP_LEVEL axi_hdmi_tx_alt
add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
add_fileset_file ad_csc_1_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_mul.v add_fileset_file ad_csc_1_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_mul.v
add_fileset_file ad_csc_1_add.v VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_add.v add_fileset_file ad_csc_1_add.v VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_add.v