altera -c5 qsys alternative
Rejeesh Kutty
parent
cc75fa3dfe
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e0459df0f3
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_in_core_c5 #(
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parameter SERDES_FACTOR = 8) (
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input clk,
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input div_clk,
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input enable,
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input data_in,
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output [(SERDES_FACTOR-1):0] data);
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reg [(SERDES_FACTOR-1):0] data_int = 'd0;
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wire [(SERDES_FACTOR-1):0] data_s;
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assign data = data_int;
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always @(posedge div_clk) begin
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data_int <= data_s;
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end
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altlvds_rx i_altlvds_rx (
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.rx_enable (enable),
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.rx_in (data_in),
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.rx_inclock (clk),
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.rx_out (data_s),
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.dpa_pll_cal_busy (),
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.dpa_pll_recal (1'b0),
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.pll_areset (1'b0),
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.pll_phasecounterselect (),
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.pll_phasedone (1'b1),
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.pll_phasestep (),
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.pll_phaseupdown (),
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.pll_scanclk (),
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.rx_cda_max (),
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.rx_cda_reset (1'b0),
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.rx_channel_data_align (1'b0),
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.rx_coreclk (1'b1),
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.rx_data_align (1'b0),
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.rx_data_align_reset (1'b0),
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.rx_data_reset (1'b0),
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.rx_deskew (1'b0),
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.rx_divfwdclk (),
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.rx_dpa_lock_reset (1'b0),
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.rx_dpa_locked (),
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.rx_dpaclock (1'b0),
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.rx_dpll_enable (1'b1),
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.rx_dpll_hold (1'b0),
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.rx_dpll_reset (1'b0),
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.rx_fifo_reset (1'b0),
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.rx_locked (),
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.rx_outclock (),
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.rx_pll_enable (1'b1),
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.rx_readclock (1'b0),
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.rx_reset (1'b0),
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.rx_syncclock (1'b0));
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defparam
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i_altlvds_rx.buffer_implementation = "RAM",
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i_altlvds_rx.cds_mode = "UNUSED",
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i_altlvds_rx.common_rx_tx_pll = "OFF",
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i_altlvds_rx.data_align_rollover = 4,
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i_altlvds_rx.data_rate = "800.0 Mbps",
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i_altlvds_rx.deserialization_factor = SERDES_FACTOR,
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i_altlvds_rx.dpa_initial_phase_value = 0,
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i_altlvds_rx.dpll_lock_count = 0,
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i_altlvds_rx.dpll_lock_window = 0,
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i_altlvds_rx.enable_clock_pin_mode = "UNUSED",
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i_altlvds_rx.enable_dpa_align_to_rising_edge_only = "OFF",
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i_altlvds_rx.enable_dpa_calibration = "ON",
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i_altlvds_rx.enable_dpa_fifo = "UNUSED",
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i_altlvds_rx.enable_dpa_initial_phase_selection = "OFF",
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i_altlvds_rx.enable_dpa_mode = "OFF",
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i_altlvds_rx.enable_dpa_pll_calibration = "OFF",
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i_altlvds_rx.enable_soft_cdr_mode = "OFF",
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i_altlvds_rx.implement_in_les = "OFF",
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i_altlvds_rx.inclock_boost = 0,
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i_altlvds_rx.inclock_data_alignment = "EDGE_ALIGNED",
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i_altlvds_rx.inclock_period = 50000,
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i_altlvds_rx.inclock_phase_shift = 0,
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i_altlvds_rx.input_data_rate = 800,
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i_altlvds_rx.intended_device_family = "Cyclone V",
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i_altlvds_rx.lose_lock_on_one_change = "UNUSED",
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i_altlvds_rx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_in_core_c5",
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i_altlvds_rx.lpm_type = "altlvds_rx",
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i_altlvds_rx.number_of_channels = 1,
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i_altlvds_rx.outclock_resource = "Dual-Regional clock",
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i_altlvds_rx.pll_operation_mode = "NORMAL",
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i_altlvds_rx.pll_self_reset_on_loss_lock = "UNUSED",
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i_altlvds_rx.port_rx_channel_data_align = "PORT_UNUSED",
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i_altlvds_rx.port_rx_data_align = "PORT_UNUSED",
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i_altlvds_rx.refclk_frequency = "20.000000 MHz",
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i_altlvds_rx.registered_data_align_input = "UNUSED",
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i_altlvds_rx.registered_output = "OFF",
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i_altlvds_rx.reset_fifo_at_first_lock = "UNUSED",
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i_altlvds_rx.rx_align_data_reg = "RISING_EDGE",
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i_altlvds_rx.sim_dpa_is_negative_ppm_drift = "OFF",
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i_altlvds_rx.sim_dpa_net_ppm_variation = 0,
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i_altlvds_rx.sim_dpa_output_clock_phase_shift = 0,
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i_altlvds_rx.use_coreclock_input = "OFF",
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i_altlvds_rx.use_dpll_rawperror = "OFF",
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i_altlvds_rx.use_external_pll = "ON",
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i_altlvds_rx.use_no_phase_shift = "ON",
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i_altlvds_rx.x_on_bitslip = "ON",
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i_altlvds_rx.clk_src_is_pll = "off";
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,107 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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||||
// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_out_core_c5 #(
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parameter SERDES_FACTOR = 8) (
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input clk,
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input div_clk,
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input enable,
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output data_out,
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input [(SERDES_FACTOR-1):0] data);
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reg [(SERDES_FACTOR-1):0] data_int = 'd0;
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always @(posedge div_clk) begin
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data_int <= data;
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end
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altlvds_tx i_altlvds_tx (
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.tx_enable (enable),
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.tx_in (data),
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.tx_inclock (clk),
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.tx_out (data_out),
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.pll_areset (1'b0),
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.sync_inclock (1'b0),
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.tx_coreclock (),
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.tx_data_reset (1'b0),
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.tx_locked (),
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.tx_outclock (),
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.tx_pll_enable (1'b1),
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.tx_syncclock (1'b0));
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defparam
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i_altlvds_tx.center_align_msb = "UNUSED",
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i_altlvds_tx.common_rx_tx_pll = "OFF",
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i_altlvds_tx.coreclock_divide_by = 1,
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i_altlvds_tx.data_rate = "800.0 Mbps",
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i_altlvds_tx.deserialization_factor = SERDES_FACTOR,
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i_altlvds_tx.differential_drive = 0,
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i_altlvds_tx.enable_clock_pin_mode = "UNUSED",
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i_altlvds_tx.implement_in_les = "OFF",
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i_altlvds_tx.inclock_boost = 0,
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i_altlvds_tx.inclock_data_alignment = "EDGE_ALIGNED",
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i_altlvds_tx.inclock_period = 50000,
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i_altlvds_tx.inclock_phase_shift = 0,
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i_altlvds_tx.intended_device_family = "Cyclone V",
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i_altlvds_tx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_out_core_c5",
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i_altlvds_tx.lpm_type = "altlvds_tx",
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i_altlvds_tx.multi_clock = "OFF",
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i_altlvds_tx.number_of_channels = 1,
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i_altlvds_tx.outclock_alignment = "EDGE_ALIGNED",
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i_altlvds_tx.outclock_divide_by = 1,
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i_altlvds_tx.outclock_duty_cycle = 50,
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i_altlvds_tx.outclock_multiply_by = 1,
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i_altlvds_tx.outclock_phase_shift = 0,
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i_altlvds_tx.outclock_resource = "Dual-Regional clock",
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i_altlvds_tx.output_data_rate = 800,
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i_altlvds_tx.pll_compensation_mode = "AUTO",
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i_altlvds_tx.pll_self_reset_on_loss_lock = "OFF",
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i_altlvds_tx.preemphasis_setting = 0,
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i_altlvds_tx.refclk_frequency = "20.000000 MHz",
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i_altlvds_tx.registered_input = "OFF",
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i_altlvds_tx.use_external_pll = "ON",
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i_altlvds_tx.use_no_phase_shift = "ON",
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i_altlvds_tx.vod_setting = 0,
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i_altlvds_tx.clk_src_is_pll = "off";
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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