jesd204: Add out of context constraint file for link layer cores

For the out of context flow it is important to have all clocks defined
at the interface, especially if the clock are used in the other constraints.

library/jesd204/jesd204_rx/Makefile

@@ -17,6 +17,7 @@ GENERIC_DEPS += jesd204_rx_lane.v
 
 XILINX_DEPS += error_monitor.v
 XILINX_DEPS += jesd204_rx_constr.ttcl
+XILINX_DEPS += jesd204_rx_ooc.ttcl
 XILINX_DEPS += jesd204_rx_ctrl_64b.v
 XILINX_DEPS += jesd204_rx_header.v
 XILINX_DEPS += jesd204_rx_ip.tcl

library/jesd204/jesd204_rx/jesd204_rx_ip.tcl

@@ -60,6 +60,7 @@ adi_ip_files jesd204_rx [list \
   "jesd204_lane_latency_monitor.v" \
   "jesd204_rx_frame_align.v" \
   "jesd204_rx_constr.ttcl" \
+  "jesd204_rx_ooc.ttcl" \
   "jesd204_rx.v" \
   "../../common/ad_pack.v" \
   "bd/bd.tcl"
@@ -67,6 +68,7 @@ adi_ip_files jesd204_rx [list \
 
 adi_ip_properties_lite jesd204_rx
 adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
+adi_ip_ttcl jesd204_rx "jesd204_rx_ooc.ttcl"
 adi_ip_bd jesd204_rx "bd/bd.tcl"
 
 adi_ip_add_core_dependencies { \

library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl

@@ -0,0 +1,40 @@
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact jesd204-licensing@analog.com for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name clk        -period 2.5 [get_ports clk]
+create_clock -name device_clk -period 2.5 [get_ports device_clk]
+
+################################################################################
+

library/jesd204/jesd204_tx/Makefile

@@ -10,6 +10,7 @@ GENERIC_DEPS += jesd204_tx_ctrl.v
 GENERIC_DEPS += jesd204_tx_lane.v
 
 XILINX_DEPS += jesd204_tx_constr.ttcl
+XILINX_DEPS += jesd204_tx_ooc.ttcl
 XILINX_DEPS += jesd204_tx_header.v
 XILINX_DEPS += jesd204_tx_ip.tcl
 XILINX_DEPS += jesd204_tx_lane_64b.v

library/jesd204/jesd204_tx/jesd204_tx_ip.tcl

@@ -53,6 +53,7 @@ adi_ip_files jesd204_tx [list \
   "jesd204_tx_gearbox.v" \
   "jesd204_tx_ctrl.v" \
   "jesd204_tx_constr.ttcl" \
+  "jesd204_tx_ooc.ttcl" \
   "../../common/ad_upack.v" \
   "jesd204_tx.v" \
   "bd/bd.tcl"
@@ -60,6 +61,7 @@ adi_ip_files jesd204_tx [list \
 
 adi_ip_properties_lite jesd204_tx
 adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
+adi_ip_ttcl jesd204_tx "jesd204_tx_ooc.ttcl"
 adi_ip_bd jesd204_tx "bd/bd.tcl"
 
 adi_ip_add_core_dependencies { \

library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl

@@ -0,0 +1,40 @@
+# along with this source code, and binary.  If not, see
+# <http://www.gnu.org/licenses/>.
+#
+# Commercial licenses (with commercial support) of this JESD204 core are also
+# available under terms different than the General Public License. (e.g. they
+# do not require you to accompany any image (FPGA or ASIC) using the JESD204
+# core with any corresponding source code.) For these alternate terms you must
+# purchase a license from Analog Devices Technology Licensing Office. Users
+# interested in such a license should contact jesd204-licensing@analog.com for
+# more information. This commercial license is sub-licensable (if you purchase
+# chips from Analog Devices, incorporate them into your PCB level product, and
+# purchase a JESD204 license, end users of your product will also have a
+# license to use this core in a commercial setting without releasing their
+# source code).
+#
+# In addition, we kindly ask you to acknowledge ADI in any program, application
+# or publication in which you use this JESD204 HDL core. (You are not required
+# to do so; it is up to your common sense to decide whether you want to comply
+# with this request or not.) For general publications, we suggest referencing :
+# “The design and implementation of the JESD204 HDL Core used in this project
+# is copyright © 2016-2017, Analog Devices, Inc.”
+#
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name clk        -period 2.5 [get_ports clk]
+create_clock -name device_clk -period 2.5 [get_ports device_clk]
+
+################################################################################
+