ad9081_fmca_ebz: Whitespace cleanup
Clear extra lines and whitespaces at end of lines.main
Laszlo Nagy
Laszlo Nagy
parent
7df4caf8b0
commit
e112a03d85
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@ -1,11 +1,11 @@
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#
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#
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# Parameter description:
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# JESD_MODE : Used link layer encoder mode
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# JESD_MODE : Used link layer encoder mode
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# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
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# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
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#
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# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
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# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
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#
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# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
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# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
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# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
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# Encoding is:
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# 0 - CPLL
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@ -18,17 +18,16 @@
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# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
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#
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# Common parameter for TX and RX
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set JESD_MODE $ad_project_params(JESD_MODE)
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set JESD_MODE $ad_project_params(JESD_MODE)
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if {$JESD_MODE == "8B10B"} {
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set DATAPATH_WIDTH 4
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set ENCODER_SEL 1
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set DATAPATH_WIDTH 4
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set ENCODER_SEL 1
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set ADI_PHY_SEL 1
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} else {
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set DATAPATH_WIDTH 8
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set ENCODER_SEL 2
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set DATAPATH_WIDTH 8
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set ENCODER_SEL 2
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set ADI_PHY_SEL 0
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}
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@ -49,7 +48,6 @@ set RX_JESD_L $ad_project_params(RX_JESD_L)
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set RX_JESD_S $ad_project_params(RX_JESD_S)
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set RX_JESD_NP $ad_project_params(RX_JESD_NP)
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set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS]
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set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS]
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set RX_SAMPLES_PER_FRAME $RX_JESD_S
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@ -57,7 +55,6 @@ set RX_SAMPLE_WIDTH $RX_JESD_NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8*$DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
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# TX parameters
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set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS)
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@ -139,11 +136,10 @@ ad_ip_instance proc_sys_reset tx_device_clk_rstgen
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ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk
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ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in
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# Common PHYs
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# Use two instances since they are located on different SLRS
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set rx_rate $ad_project_params(RX_RATE)
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set tx_rate $ad_project_params(TX_RATE)
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set rx_rate $ad_project_params(RX_RATE)
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set tx_rate $ad_project_params(TX_RATE)
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set ref_clk_rate $ad_project_params(REF_CLK_RATE)
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ad_ip_instance jesd204_phy jesd204_phy_121 [list \
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@ -187,7 +183,6 @@ ad_ip_instance jesd204_phy jesd204_phy_126 [list \
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# adc peripherals
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adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL
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ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false
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@ -221,8 +216,6 @@ ad_ip_parameter axi_mxfe_rx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
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ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width
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# dac peripherals
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adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL
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@ -276,11 +269,9 @@ for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} {
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ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_*
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ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} rx_device_clk
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@ -333,7 +324,7 @@ if {$ADI_PHY_SEL == 0} {
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ad_connect $sys_cpu_reset jesd204_phy_121/tx_sys_reset
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ad_connect $sys_cpu_reset jesd204_phy_126/tx_sys_reset
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ad_connect $sys_cpu_reset jesd204_phy_121/rx_sys_reset
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ad_connect $sys_cpu_reset jesd204_phy_121/rx_sys_reset
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ad_connect $sys_cpu_reset jesd204_phy_126/rx_sys_reset
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ad_connect axi_mxfe_tx_jesd/tx_axi/core_reset jesd204_phy_121/tx_reset_gt
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@ -391,7 +382,6 @@ for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} {
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ad_connect axi_mxfe_rx_jesd/rx_phy$j $logic_lane($j)
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}
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ad_connect rx_sysref_0 axi_mxfe_rx_jesd/sysref
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}
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@ -416,7 +406,6 @@ ad_connect mxfe_adc_fifo/dma_wdata axi_mxfe_rx_dma/s_axis_data
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ad_connect mxfe_adc_fifo/dma_wready axi_mxfe_rx_dma/s_axis_ready
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ad_connect mxfe_adc_fifo/dma_xfer_req axi_mxfe_rx_dma/s_axis_xfer_req
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# connect dac dataflow
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#
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if {$ADI_PHY_SEL == 0} {
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@ -444,7 +433,6 @@ for {set i 0} {$i < 4} {incr i} {
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ad_connect jesd204_phy_126/txp_out txp_out_slice_[expr $i+4]/Din
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}
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for {set i 0} {$i < $MAX_TX_LANES} {incr i} {
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ad_connect txn_out_slice_$i/Dout tx_data_${i}_n
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ad_connect txp_out_slice_$i/Dout tx_data_${i}_p
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@ -492,7 +480,6 @@ ad_connect mxfe_dac_fifo/dac_dunf tx_mxfe_tpl_core/dac_dunf
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create_bd_port -dir I dac_fifo_bypass
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ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass
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# interconnect (cpu)
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if {$ADI_PHY_SEL == 1} {
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ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr
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@ -527,7 +514,6 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
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ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq
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ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
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if {$ADI_PHY_SEL == 1} {
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# Create dummy outputs for unused Tx lanes
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for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} {
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