From e112a03d8596e5aba78253e93177d0cb5bd275f6 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 21 Apr 2020 16:17:01 +0100 Subject: [PATCH] ad9081_fmca_ebz: Whitespace cleanup Clear extra lines and whitespaces at end of lines. --- .../common/ad9081_fmca_ebz_bd.tcl | 40 ++++++------------- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl index ac32ad542..fbdcfd69d 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl @@ -1,11 +1,11 @@ -# +# # Parameter description: -# JESD_MODE : Used link layer encoder mode +# JESD_MODE : Used link layer encoder mode # 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer # 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer -# -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode +# +# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode +# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode # [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode # Encoding is: # 0 - CPLL @@ -18,17 +18,16 @@ # [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # - # Common parameter for TX and RX -set JESD_MODE $ad_project_params(JESD_MODE) +set JESD_MODE $ad_project_params(JESD_MODE) if {$JESD_MODE == "8B10B"} { - set DATAPATH_WIDTH 4 - set ENCODER_SEL 1 + set DATAPATH_WIDTH 4 + set ENCODER_SEL 1 set ADI_PHY_SEL 1 } else { - set DATAPATH_WIDTH 8 - set ENCODER_SEL 2 + set DATAPATH_WIDTH 8 + set ENCODER_SEL 2 set ADI_PHY_SEL 0 } @@ -49,7 +48,6 @@ set RX_JESD_L $ad_project_params(RX_JESD_L) set RX_JESD_S $ad_project_params(RX_JESD_S) set RX_JESD_NP $ad_project_params(RX_JESD_NP) - set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] set RX_SAMPLES_PER_FRAME $RX_JESD_S @@ -57,7 +55,6 @@ set RX_SAMPLE_WIDTH $RX_JESD_NP set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8*$DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] - # TX parameters set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) @@ -139,11 +136,10 @@ ad_ip_instance proc_sys_reset tx_device_clk_rstgen ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in - # Common PHYs # Use two instances since they are located on different SLRS -set rx_rate $ad_project_params(RX_RATE) -set tx_rate $ad_project_params(TX_RATE) +set rx_rate $ad_project_params(RX_RATE) +set tx_rate $ad_project_params(TX_RATE) set ref_clk_rate $ad_project_params(REF_CLK_RATE) ad_ip_instance jesd204_phy jesd204_phy_121 [list \ @@ -187,7 +183,6 @@ ad_ip_instance jesd204_phy jesd204_phy_126 [list \ # adc peripherals - adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false @@ -221,8 +216,6 @@ ad_ip_parameter axi_mxfe_rx_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width - - # dac peripherals adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL @@ -276,11 +269,9 @@ for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} { ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_* ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_* - ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk - # connections (adc) ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} rx_device_clk @@ -333,7 +324,7 @@ if {$ADI_PHY_SEL == 0} { ad_connect $sys_cpu_reset jesd204_phy_121/tx_sys_reset ad_connect $sys_cpu_reset jesd204_phy_126/tx_sys_reset -ad_connect $sys_cpu_reset jesd204_phy_121/rx_sys_reset +ad_connect $sys_cpu_reset jesd204_phy_121/rx_sys_reset ad_connect $sys_cpu_reset jesd204_phy_126/rx_sys_reset ad_connect axi_mxfe_tx_jesd/tx_axi/core_reset jesd204_phy_121/tx_reset_gt @@ -391,7 +382,6 @@ for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} { ad_connect axi_mxfe_rx_jesd/rx_phy$j $logic_lane($j) } - ad_connect rx_sysref_0 axi_mxfe_rx_jesd/sysref } @@ -416,7 +406,6 @@ ad_connect mxfe_adc_fifo/dma_wdata axi_mxfe_rx_dma/s_axis_data ad_connect mxfe_adc_fifo/dma_wready axi_mxfe_rx_dma/s_axis_ready ad_connect mxfe_adc_fifo/dma_xfer_req axi_mxfe_rx_dma/s_axis_xfer_req - # connect dac dataflow # if {$ADI_PHY_SEL == 0} { @@ -444,7 +433,6 @@ for {set i 0} {$i < 4} {incr i} { ad_connect jesd204_phy_126/txp_out txp_out_slice_[expr $i+4]/Din } - for {set i 0} {$i < $MAX_TX_LANES} {incr i} { ad_connect txn_out_slice_$i/Dout tx_data_${i}_n ad_connect txp_out_slice_$i/Dout tx_data_${i}_p @@ -492,7 +480,6 @@ ad_connect mxfe_dac_fifo/dac_dunf tx_mxfe_tpl_core/dac_dunf create_bd_port -dir I dac_fifo_bypass ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass - # interconnect (cpu) if {$ADI_PHY_SEL == 1} { ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr @@ -527,7 +514,6 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq - if {$ADI_PHY_SEL == 1} { # Create dummy outputs for unused Tx lanes for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} {