From e15893444cfbb2e31c513712b6d9c0e5f7c8f3a8 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 16 May 2016 13:28:24 -0400 Subject: [PATCH] upack- fix interface names --- library/util_upack/util_upack_hw.tcl | 119 +++++++++++++++------------ 1 file changed, 67 insertions(+), 52 deletions(-) diff --git a/library/util_upack/util_upack_hw.tcl b/library/util_upack/util_upack_hw.tcl index 0217d3734..c7444712d 100755 --- a/library/util_upack/util_upack_hw.tcl +++ b/library/util_upack/util_upack_hw.tcl @@ -39,76 +39,91 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # defaults ad_alt_intf clock dac_clk input 1 -ad_alt_intf signal dma_xfer_in input 1 xfer_req -ad_alt_intf signal dac_xfer_out output 1 xfer_req -ad_alt_intf signal dac_valid output 1 valid -ad_alt_intf signal dac_sync output 1 sync + +ad_alt_intf signal dma_xfer_in input 1 xfer_req +ad_alt_intf signal dac_xfer_out output 1 xfer_req + +ad_alt_intf signal dac_valid output 1 valid +ad_alt_intf signal dac_sync output 1 sync ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data -add_interface fifo_ch_0 conduit end -#set_interface_property fifo_ch_0 associatedClock if_dac_clk -add_interface_port fifo_ch_0 dac_enable_0 enable Input 1 -add_interface_port fifo_ch_0 dac_valid_0 valid Input 1 -#add_interface_port fifo_ch_0 upack_valid_0 valid_o Output 1 -add_interface_port fifo_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_0 enable Input 1 +add_interface_port dac_ch_0 dac_valid_0 valid Input 1 +add_interface_port dac_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH + +set_interface_property dac_ch_0 associatedClock if_dac_clk proc p_util_upack {} { if {[get_parameter_value NUM_OF_CHANNELS] > 1} { - add_interface fifo_ch_1 conduit end - #set_interface_property fifo_ch_1 associatedClock if_dac_clk - add_interface_port fifo_ch_1 dac_enable_1 enable Input 1 - add_interface_port fifo_ch_1 dac_valid_1 valid Input 1 -# add_interface_port fifo_ch_1 upack_valid_1 valid_o Output 1 - add_interface_port fifo_ch_1 dac_data_1 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_1 conduit end + add_interface_port dac_ch_1 dac_enable_1 enable Input 1 + add_interface_port dac_ch_1 dac_valid_1 valid Input 1 + add_interface_port dac_ch_1 dac_data_1 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_1 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { - add_interface fifo_ch_2 conduit end - #set_interface_property fifo_ch_2 associatedClock if_dac_clk - add_interface_port fifo_ch_2 dac_enable_2 enable Input 1 - add_interface_port fifo_ch_2 dac_valid_2 valid Input 1 -# add_interface_port fifo_ch_2 upack_valid_2 valid_o Output 1 - add_interface_port fifo_ch_2 dac_data_2 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_2 conduit end + add_interface_port dac_ch_2 dac_enable_2 enable Input 1 + add_interface_port dac_ch_2 dac_valid_2 valid Input 1 + add_interface_port dac_ch_2 dac_data_2 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_2 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { - add_interface fifo_ch_3 conduit end - #set_interface_property fifo_ch_3 associatedClock if_dac_clk - add_interface_port fifo_ch_3 dac_enable_3 enable Input 1 - add_interface_port fifo_ch_3 dac_valid_3 valid Input 1 -# add_interface_port fifo_ch_3 upack_valid_3 valid_o Output 1 - add_interface_port fifo_ch_3 dac_data_3 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_3 conduit end + add_interface_port dac_ch_3 dac_enable_3 enable Input 1 + add_interface_port dac_ch_3 dac_valid_3 valid Input 1 + add_interface_port dac_ch_3 dac_data_3 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_3 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { - add_interface fifo_ch_4 conduit end - #set_interface_property fifo_ch_4 associatedClock if_dac_clk - add_interface_port fifo_ch_4 dac_enable_4 enable Input 1 - add_interface_port fifo_ch_4 dac_valid_4 valid Input 1 -# add_interface_port fifo_ch_4 upack_valid_4 valid_o Output 1 - add_interface_port fifo_ch_4 dac_data_4 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_4 conduit end + add_interface_port dac_ch_4 dac_enable_4 enable Input 1 + add_interface_port dac_ch_4 dac_valid_4 valid Input 1 + add_interface_port dac_ch_4 dac_data_4 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_4 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { - add_interface fifo_ch_5 conduit end - #set_interface_property fifo_ch_5 associatedClock if_dac_clk - add_interface_port fifo_ch_5 dac_enable_5 enable Input 1 - add_interface_port fifo_ch_5 dac_valid_5 valid Input 1 -# add_interface_port fifo_ch_5 upack_valid_5 valid_o Output 1 - add_interface_port fifo_ch_5 dac_data_5 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_5 conduit end + add_interface_port dac_ch_5 dac_enable_5 enable Input 1 + add_interface_port dac_ch_5 dac_valid_5 valid Input 1 + add_interface_port dac_ch_5 dac_data_5 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_5 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { - add_interface fifo_ch_6 conduit end - #set_interface_property fifo_ch_6 associatedClock if_dac_clk - add_interface_port fifo_ch_6 dac_enable_6 enable Input 1 - add_interface_port fifo_ch_6 dac_valid_6 valid Input 1 -# add_interface_port fifo_ch_6 upack_valid_6 valid_o Output 1 - add_interface_port fifo_ch_6 dac_data_6 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_6 conduit end + add_interface_port dac_ch_6 dac_enable_6 enable Input 1 + add_interface_port dac_ch_6 dac_valid_6 valid Input 1 + add_interface_port dac_ch_6 dac_data_6 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_6 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { - add_interface fifo_ch_7 conduit end - #set_interface_property fifo_ch_7 associatedClock if_dac_clk - add_interface_port fifo_ch_7 dac_enable_7 enable Input 1 - add_interface_port fifo_ch_7 dac_valid_7 valid Input 1 -# add_interface_port fifo_ch_7 upack_valid_7 valid_o Output 1 - add_interface_port fifo_ch_7 dac_data_7 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_7 conduit end + add_interface_port dac_ch_7 dac_enable_7 enable Input 1 + add_interface_port dac_ch_7 dac_valid_7 valid Input 1 + add_interface_port dac_ch_7 dac_data_7 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_7 associatedClock if_dac_clk } }