From e15f0cd2c64c0cc4ad67b2421920946f2ea885f5 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 19 Feb 2015 14:11:58 +0100
Subject: [PATCH] dmac: fifo_inf: Handle overflow and underflow correctly

Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/dest_fifo_inf.v | 25 ++++++++++---------------
 library/axi_dmac/src_fifo_inf.v  | 29 +++++------------------------
 2 files changed, 15 insertions(+), 39 deletions(-)

diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v
index 20ecf2c88..acd527978 100644
--- a/library/axi_dmac/dest_fifo_inf.v
+++ b/library/axi_dmac/dest_fifo_inf.v
@@ -53,8 +53,8 @@ module dmac_dest_fifo_inf (
 
 	input en,
 	output [C_DATA_WIDTH-1:0] dout,
-	output reg valid,
-	output reg underflow,
+	output valid,
+	output underflow,
 
 	output fifo_ready,
 	input fifo_valid,
@@ -80,28 +80,23 @@ wire data_enabled;
 wire _fifo_ready;
 assign fifo_ready = _fifo_ready | ~enabled;
 
-reg data_ready;
+reg en_d1;
+wire data_ready;
 wire data_valid;
 
 always @(posedge clk)
 begin
 	if (resetn == 1'b0) begin
-		data_ready <= 1'b1;
-		underflow <= 1'b0;
-		valid <= 1'b0;
+		en_d1 <= 1'b0;
 	end else begin
-		if (enable == 1'b1) begin
-			valid <= data_valid & en;
-			data_ready <= en & data_valid;
-			underflow <= en & ~data_valid;
-		end else begin
-			valid <= 1'b0;
-			data_ready <= 1'b1;
-			underflow <= en;
-		end
+		en_d1 <= en;
 	end
 end
 
+assign underflow = en_d1 & (~data_valid | ~enable);
+assign data_ready = en_d1 & (data_valid | ~enable);
+assign valid = en_d1 & data_valid & enable;
+
 dmac_data_mover # (
 	.C_ID_WIDTH(C_ID_WIDTH),
 	.C_DATA_WIDTH(C_DATA_WIDTH),
diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v
index fedf7fb54..449e064a0 100644
--- a/library/axi_dmac/src_fifo_inf.v
+++ b/library/axi_dmac/src_fifo_inf.v
@@ -69,21 +69,18 @@ parameter C_ID_WIDTH = 3;
 parameter C_DATA_WIDTH = 64;
 parameter C_BEATS_PER_BURST_WIDTH = 4;
 
-reg valid = 1'b0;
 wire ready;
-reg [C_DATA_WIDTH-1:0] buffer = 'h00;
-reg buffer_sync = 1'b0;
 
 reg needs_sync = 1'b0;
-wire has_sync = ~needs_sync | buffer_sync;
-wire sync_valid = valid & has_sync;
+wire has_sync = ~needs_sync | sync;
+wire sync_valid = en & ready & has_sync;
 
 always @(posedge clk)
 begin
 	if (resetn == 1'b0) begin
 		needs_sync <= 1'b0;
 	end else begin
-		if (ready && valid && buffer_sync) begin
+		if (ready && en && sync) begin
 			needs_sync <= 1'b0;
 		end else if (req_valid && req_ready) begin
 			needs_sync <= req_sync_transfer_start;
@@ -91,30 +88,14 @@ begin
 	end
 end
 
-always @(posedge clk)
-begin
-	if (en) begin
-		buffer <= din;
-		buffer_sync <= sync;
-	end
-end
-
 always @(posedge clk)
 begin
 	if (resetn == 1'b0) begin
-		valid <= 1'b0;
 		overflow <= 1'b0;
 	end else begin
 		if (enable) begin
-			if (en) begin
-				valid <= 1'b1;
-			end else if (ready || ~xfer_req) begin
-				valid <= 1'b0;
-			end
-			overflow <= en & valid & ~ready;
+			overflow <= en & ~ready;
 		end else begin
-			if (ready || ~xfer_req)
-				valid <= 1'b0;
 			overflow <= en;
 		end
 	end
@@ -147,7 +128,7 @@ dmac_data_mover # (
 
 	.s_axi_ready(ready),
 	.s_axi_valid(sync_valid),
-	.s_axi_data(buffer),
+	.s_axi_data(din),
 	.m_axi_ready(fifo_ready),
 	.m_axi_valid(fifo_valid),
 	.m_axi_data(fifo_data),