From e1829a061d8ea891c1ce599b0899921e3c172804 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 30 Jun 2021 17:15:42 -0500 Subject: [PATCH] adrv9001: fixes for reset metastability on xilinx ioserdes * fixes DRC warning that the clocking configuration may result in data errors * fixes ioserdes reset issue with synchronous de-assert in data clock domain --- library/axi_adrv9001/adrv9001_rx.v | 18 ++++++++++++++++-- library/axi_adrv9001/adrv9001_tx.v | 17 +++++++++++++++-- library/xilinx/common/ad_serdes_in.v | 13 +++++++++++-- library/xilinx/common/ad_serdes_out.v | 13 +++++++++++-- 4 files changed, 53 insertions(+), 8 deletions(-) diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v index de15969b1..e9ce77831 100644 --- a/library/axi_adrv9001/adrv9001_rx.v +++ b/library/axi_adrv9001/adrv9001_rx.v @@ -200,12 +200,26 @@ module adrv9001_rx #( .CE (1'b1), .I (clk_in_s), .O (adc_clk_div_s)); - + /* BUFG I_bufg ( .I (adc_clk_div_s), .O (adc_clk_div) ); - assign ssi_rst = mssi_sync; + */ + assign adc_clk_div = adc_clk_div_s; + + xpm_cdc_async_rst + # ( + .DEST_SYNC_FF (10), // DECIMAL; range: 2-10 + .INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset + ) + rst_syncro + ( + .src_arst (mssi_sync ), + .dest_clk (adc_clk_div), + .dest_arst(ssi_rst ) + ); end else begin wire adc_clk_in; diff --git a/library/axi_adrv9001/adrv9001_tx.v b/library/axi_adrv9001/adrv9001_tx.v index 07cf0173f..619fc37da 100644 --- a/library/axi_adrv9001/adrv9001_tx.v +++ b/library/axi_adrv9001/adrv9001_tx.v @@ -188,13 +188,26 @@ module adrv9001_tx #( .CE (1'b1), .I (tx_dclk_in_s), .O (dac_clk_div_s)); - +/* BUFG I_bufg ( .I (dac_clk_div_s), .O (dac_clk_div) ); +*/ + assign dac_clk_div = dac_clk_div_s; - assign ssi_rst = mssi_sync; + xpm_cdc_async_rst + # ( + .DEST_SYNC_FF (10), // DECIMAL; range: 2-10 + .INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset + ) + rst_syncro + ( + .src_arst (mssi_sync ), + .dest_clk (dac_clk_div), + .dest_arst(ssi_rst ) + ); end else begin diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v index d19a96cd9..d4e1b20da 100644 --- a/library/xilinx/common/ad_serdes_in.v +++ b/library/xilinx/common/ad_serdes_in.v @@ -137,6 +137,15 @@ module ad_serdes_in #( end endgenerate + reg [6:0] serdes_rst_seq; + wire serdes_rst = serdes_rst_seq [6]; + + always @ (posedge div_clk) + begin + if (rst) serdes_rst_seq [6:0] <= 7'b0001110; + else serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + end + generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data @@ -208,7 +217,7 @@ module ad_serdes_in #( .DDLY (data_in_idelay_s[l_inst]), .OFB (1'b0), .OCLKB (1'b0), - .RST (rst), + .RST (serdes_rst), .SHIFTIN1 (1'b0), .SHIFTIN2 (1'b0)); end /* g_data */ @@ -303,7 +312,7 @@ module ad_serdes_in #( .D (data_in_idelay_s[l_inst]), // 1-bit input: Serial Data Input .FIFO_RD_CLK (div_clk), // 1-bit input: FIFO read clock .FIFO_RD_EN (1'b1), // 1-bit input: Enables reading the FIFO when asserted - .RST (rst) // 1-bit input: Asynchronous Reset + .RST (serdes_rst) // 1-bit input: Asynchronous Reset ); end end diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v index 26bb77bf2..adb3b51dd 100644 --- a/library/xilinx/common/ad_serdes_out.v +++ b/library/xilinx/common/ad_serdes_out.v @@ -89,6 +89,15 @@ module ad_serdes_out #( assign buffer_disable = ~data_oe; // instantiations + reg [6:0] serdes_rst_seq; + wire serdes_rst = serdes_rst_seq [6]; + + always @ (posedge div_clk) + begin + if (rst) serdes_rst_seq [6:0] <= 7'b0001110; + else serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + end + genvar l_inst; generate for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data @@ -127,7 +136,7 @@ module ad_serdes_out #( .TBYTEIN (1'b0), .TBYTEOUT (), .TCE (1'b1), - .RST (rst & data_oe)); + .RST (serdes_rst)); end if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin @@ -148,7 +157,7 @@ module ad_serdes_out #( .CLKDIV (div_clk), .OQ (data_out_s[l_inst]), .T_OUT (data_t[l_inst]), - .RST (rst & data_oe)); + .RST (serdes_rst)); end if (CMOS_LVDS_N == 0) begin