From 6da9c65a08af334f13fd1ded1ca4c05573bf4da8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 29 Jan 2014 13:35:17 +0100 Subject: [PATCH 1/4] axi_dmac: Add support for zero latency transfer switching Right now there is always a period of one clock cycle where we can not transfer any data when switching between two transfers. This patch modifies the data mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/data_mover.v | 51 +++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index e72568f6a..1ef496710 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -58,7 +58,7 @@ module dmac_data_mover ( output m_axi_last, input req_valid, - output reg req_ready, + output req_ready, input [3:0] req_last_burst_length ); @@ -72,20 +72,25 @@ reg [3:0] last_burst_length; reg [C_ID_WIDTH-1:0] id = 'h00; reg [C_ID_WIDTH-1:0] id_next; reg [3:0] beat_counter = 'h00; -wire [3:0] beat_counter_next; wire last; +wire last_load; reg pending_burst; +reg active; assign response_id = id; -assign beat_counter_next = s_axi_ready && s_axi_valid ? beat_counter + 1'b1 : beat_counter; assign last = beat_counter == (eot ? last_burst_length : 4'hf); -assign s_axi_ready = m_axi_ready & pending_burst & ~req_ready; -assign m_axi_valid = s_axi_valid & pending_burst & ~req_ready; +assign s_axi_ready = m_axi_ready & pending_burst & active; +assign m_axi_valid = s_axi_valid & pending_burst & active; assign m_axi_data = s_axi_data; assign m_axi_last = last; +// If we want to support zero delay between transfers we have to assert +// req_ready on the same cycle on which the last load happens. +assign last_load = s_axi_ready && s_axi_valid && last && eot; +assign req_ready = last_load || ~active; + always @(posedge clk) begin if (resetn == 1'b0) begin enabled <= 1'b0; @@ -111,20 +116,31 @@ end always @(posedge clk) begin if (resetn == 1'b0) begin beat_counter <= 'h0; - req_ready <= 1'b1; + end else begin + if (req_ready && req_valid) begin + beat_counter <= 'h0; + end else if (s_axi_ready && s_axi_valid) begin + beat_counter <= beat_counter + 1'b1; + end + end +end + +always @(posedge clk) begin + if (req_ready && req_valid) begin + last_burst_length <= req_last_burst_length; + end +end + +always @(posedge clk) begin + if (resetn == 1'b0) begin + active <= 1'b0; end else begin if (~enabled) begin - req_ready <= 1'b1; - end else if (req_ready) begin - if (req_valid && enabled) begin - last_burst_length <= req_last_burst_length; - req_ready <= 1'b0; - beat_counter <= 'h0; - end - end else if (s_axi_ready && s_axi_valid) begin - if (last && eot) - req_ready <= 1'b1; - beat_counter <= beat_counter + 1'b1; + active <= 1'b0; + end else if (req_ready && req_valid) begin + active <= 1'b1; + end else if (last_load) begin + active <= 1'b0; end end end @@ -141,6 +157,7 @@ end always @(posedge clk) begin if (resetn == 1'b0) begin id <= 'h0; + pending_burst <= 1'b0; end else begin id <= id_next; pending_burst <= id_next != request_id; From 8326022adcecfbb05cc3823ef28c4da5e779becd Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 6 Mar 2014 21:58:03 +0100 Subject: [PATCH 2/4] axi_dmac: address_generator: Fix disable race condition If the address generator is disabled the very same cycle as it tries to put a new address on the bus, it will keep sending this address forever and the core will lock up Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/address_generator.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 7be066f80..4d7bbca36 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -115,7 +115,7 @@ always @(posedge clk) begin addr_valid <= 1'b0; if (eot) req_ready <= 1'b1; - end else if (id != wait_id) begin + end else if (id != wait_id && enable) begin addr_valid <= 1'b1; end end From 75963ab3761f38b8d430bfc268d1b5dc9be59f4b Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 10 Mar 2014 17:26:17 +0200 Subject: [PATCH 3/4] Initial check in of VC707 base project - All source files for the VC707 base project - Update the common base system to the new naming convention --- projects/adv7511/vc707/system_bd.tcl | 8 + projects/adv7511/vc707/system_project.tcl | 11 + projects/adv7511/vc707/system_top.v | 197 +++++++ projects/common/vc707/vc707_system_bd.tcl | 569 ++++++++++----------- projects/common/vc707/vc707_system_mig.prj | 245 ++++----- 5 files changed, 623 insertions(+), 407 deletions(-) create mode 100644 projects/adv7511/vc707/system_bd.tcl create mode 100644 projects/adv7511/vc707/system_project.tcl create mode 100644 projects/adv7511/vc707/system_top.v diff --git a/projects/adv7511/vc707/system_bd.tcl b/projects/adv7511/vc707/system_bd.tcl new file mode 100644 index 000000000..c6bbf38eb --- /dev/null +++ b/projects/adv7511/vc707/system_bd.tcl @@ -0,0 +1,8 @@ + +source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl +set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect +set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect +set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect +set_property -dict [list CONFIG.NUM_PORTS {10}] $sys_concat_intc + + diff --git a/projects/adv7511/vc707/system_project.tcl b/projects/adv7511/vc707/system_project.tcl new file mode 100644 index 000000000..64194c363 --- /dev/null +++ b/projects/adv7511/vc707/system_project.tcl @@ -0,0 +1,11 @@ + +source ../../scripts/adi_env.tcl +source ${ad_hdl_dir}/projects/scripts/adi_project.tcl + +adi_project_create adv7511_vc707 +adi_project_files adv7511_vc707 [list \ + "system_top.v" \ + "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] + +adi_project_run adv7511_vc707 + diff --git a/projects/adv7511/vc707/system_top.v b/projects/adv7511/vc707/system_top.v new file mode 100644 index 000000000..d4cd7a819 --- /dev/null +++ b/projects/adv7511/vc707/system_top.v @@ -0,0 +1,197 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_rst, + sys_clk_p, + sys_clk_n, + + uart_sin, + uart_sout, + + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + ddr3_ras_n, + ddr3_reset_n, + ddr3_we_n, + + sgmii_rxp, + sgmii_rxn, + sgmii_txp, + sgmii_txn, + + phy_rstn, + mgt_clk_p, + mgt_clk_n, + mdio_mdc, + mdio_mdio, + + fan_pwm, + + gpio_lcd, + gpio_led, + gpio_sw, + + iic_rstn, + iic_scl, + iic_sda, + + hdmi_out_clk, + hdmi_hsync, + hdmi_vsync, + hdmi_data_e, + hdmi_data, + + spdif); + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + input uart_sin; + output uart_sout; + + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + output ddr3_ras_n; + output ddr3_reset_n; + output ddr3_we_n; + + input sgmii_rxp; + input sgmii_rxn; + output sgmii_txp; + output sgmii_txn; + + output phy_rstn; + input mgt_clk_p; + input mgt_clk_n; + output mdio_mdc; + inout mdio_mdio; + + output fan_pwm; + + output [ 6:0] gpio_lcd; + output [ 7:0] gpio_led; + input [12:0] gpio_sw; + + output iic_rstn; + inout iic_scl; + inout iic_sda; + + output hdmi_out_clk; + output hdmi_hsync; + output hdmi_vsync; + output hdmi_data_e; + output [35:0] hdmi_data; + + output spdif; + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .fan_pwm (fan_pwm), + .gpio_lcd_tri_o (gpio_lcd), + .gpio_led_tri_o (gpio_led), + .gpio_sw_tri_i (gpio_sw), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .iic_rstn (iic_rstn), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .mgt_clk_clk_n (mgt_clk_n), + .mgt_clk_clk_p (mgt_clk_p), + .phy_rstn (phy_rstn), + .sgmii_rxn (sgmii_rxn), + .sgmii_rxp (sgmii_rxp), + .sgmii_txn (sgmii_txn), + .sgmii_txp (sgmii_txp), + .spdif (spdif), + .sys_clk_n (sys_clk_n), + .sys_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .uart_sin (uart_sin), + .uart_sout (uart_sout)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index c63e54bdf..776750855 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -14,7 +14,7 @@ set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw] set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led] set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd] - + set iic_rstn [create_bd_port -dir O iic_rstn] set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main] @@ -35,116 +35,108 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst # instance: microblaze - processor -set microblaze_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 microblaze_1] -set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $microblaze_1 -set_property -dict [list CONFIG.C_D_AXI {1}] $microblaze_1 -set_property -dict [list CONFIG.C_D_LMB {1}] $microblaze_1 -set_property -dict [list CONFIG.C_I_LMB {1}] $microblaze_1 -set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $microblaze_1 -set_property -dict [list CONFIG.C_USE_ICACHE {1}] $microblaze_1 -set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $microblaze_1 -set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $microblaze_1 -set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1 -set_property -dict [list CONFIG.C_USE_DCACHE {1}] $microblaze_1 -set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $microblaze_1 -set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $microblaze_1 -set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1 -set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1 -set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $microblaze_1 -set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1 -set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $microblaze_1 +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 sys_mb] +set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb +set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb +set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb +set_property -dict [list CONFIG.C_I_LMB {1}] $sys_mb +set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $sys_mb +set_property -dict [list CONFIG.C_USE_ICACHE {1}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb +set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb # instance: microblaze - local memory & bus -set dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb] -set ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb] +set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb] +set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb] -set dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_cntlr] -set_property -dict [list CONFIG.C_ECC {0}] $dlmb_cntlr +set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr] +set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr -set ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_cntlr] -set_property -dict [list CONFIG.C_ECC {0}] $ilmb_cntlr +set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] +set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 lmb_bram] -set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $lmb_bram +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 sys_lmb_bram] +set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm -set mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 mb_debug] -set_property -dict [list CONFIG.C_USE_UART {1}] $mb_debug +set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 sys_mb_debug] +set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug # instance: system reset/clocks -set proc_sys_reset_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1] +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] -set proc_sys_clock_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 proc_sys_clock_1] -set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000}] $proc_sys_clock_1 -set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100}] $proc_sys_clock_1 -set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer}] $proc_sys_clock_1 -set_property -dict [list CONFIG.USE_RESET {false}] $proc_sys_clock_1 -set_property -dict [list CONFIG.CLKOUT2_USED {true}] $proc_sys_clock_1 -set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000}] $proc_sys_clock_1 - -set proc_const_vcc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 proc_const_vcc_1] +set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] # instance: ddr (mig) -set axi_ddr_cntrl_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl_1] -set axi_ddr_cntrl_1_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl_1]]] -file copy -force ../../scripts/vc707_system_mig.prj "$axi_ddr_cntrl_1_dir/" -set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl_1 -set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl_1 +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl] +set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] +file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" +set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl +set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl # instance: axi interconnect (lite) -set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1] -set_property -dict [list CONFIG.NUM_MI {14}] $axi_interconnect_1 +set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] +set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect # instance: axi interconnect -set axi_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2] -set_property -dict [list CONFIG.NUM_SI {8}] $axi_interconnect_2 -set_property -dict [list CONFIG.NUM_MI {1}] $axi_interconnect_2 -set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_interconnect_2 -set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_interconnect_2 +set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect] +set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect +set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect +set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect +set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect # instance: default peripherals -set axi_ethernet_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.0 axi_ethernet_1] -set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet_1 +set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.0 axi_ethernet] +set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet -set axi_ethernet_dma_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma_1] -set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma_1 -set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma_1 -set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma_1 +set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma] +set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma +set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma +set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma -set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1] +set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] -set axi_uart_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart_1] -set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart_1 +set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart] +set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart -set axi_timer_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1] +set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer] -set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1] -set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_1 -set_property -dict [list CONFIG.C_ALL_OUTPUTS {1}] $axi_gpio_1 -set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_1 +set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd] +set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd +set_property -dict [list CONFIG.C_ALL_OUTPUTS {1}] $axi_gpio_lcd +set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd -set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2] -set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2 -set_property -dict [list CONFIG.C_GPIO_WIDTH {13}] $axi_gpio_2 -set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_2 -set_property -dict [list CONFIG.C_ALL_INPUTS {1}] $axi_gpio_2 -set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_2 -set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_2 +set axi_gpio_sw_led [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw_led] +set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_sw_led +set_property -dict [list CONFIG.C_GPIO_WIDTH {13}] $axi_gpio_sw_led +set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_sw_led +set_property -dict [list CONFIG.C_ALL_INPUTS {1}] $axi_gpio_sw_led +set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led +set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_sw_led # instance: interrupt -set axi_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1] -set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc_1 +set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc] +set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc -set concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 concat_intc_1] -set_property -dict [list CONFIG.NUM_PORTS {10}] $concat_intc_1 +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {10}] $sys_concat_intc # hdmi peripherals @@ -174,211 +166,218 @@ set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dm # connections -connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug/Debug_SYS_Rst] -connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins proc_sys_reset_1/mb_debug_sys_rst] +connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst] +connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst] -connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins proc_sys_reset_1/mb_reset] -connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins microblaze_1/Reset] +connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset] +connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset] -connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins proc_sys_reset_1/bus_struct_reset] -connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb/SYS_Rst] -connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb/SYS_Rst] -connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb_cntlr/LMB_Rst] -connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb_cntlr/LMB_Rst] +connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset] +connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst] +connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst] +connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst] +connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst] # microblaze local memory -connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins dlmb/LMB_Sl_0] [get_bd_intf_pins dlmb_cntlr/SLMB] -connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins ilmb/LMB_Sl_0] [get_bd_intf_pins ilmb_cntlr/SLMB] -connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] -connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] -connect_bd_intf_net -intf_net microblaze_1_dlmb [get_bd_intf_pins microblaze_1/DLMB] [get_bd_intf_pins dlmb/LMB_M] -connect_bd_intf_net -intf_net microblaze_1_ilmb [get_bd_intf_pins microblaze_1/ILMB] [get_bd_intf_pins ilmb/LMB_M] +connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB] +connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB] +connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA] +connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB] +connect_bd_intf_net -intf_net sys_mb_dlmb [get_bd_intf_pins sys_mb/DLMB] [get_bd_intf_pins sys_dlmb/LMB_M] +connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd_intf_pins sys_ilmb/LMB_M] # microblaze debug & interrupt -connect_bd_intf_net -intf_net microblaze_1_debug [get_bd_intf_pins mb_debug/MBDEBUG_0] [get_bd_intf_pins microblaze_1/DEBUG] -connect_bd_net -net concat_intc_1_intr [get_bd_pins concat_intc_1/dout] [get_bd_pins axi_intc_1/intr] -connect_bd_intf_net -intf_net microblaze_1_interrupt [get_bd_intf_pins axi_intc_1/interrupt] [get_bd_intf_pins microblaze_1/INTERRUPT] +connect_bd_intf_net -intf_net sys_mb_debug [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG] +connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr] +connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT] # defaults (peripherals) -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] +connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_rstgen/dcm_locked] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins mb_debug/S_AXI_ARESETN] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ddr_cntrl_1/aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernet_1/s_axi_lite_resetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_uart_1/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_timer_1/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_1/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_2/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_iic_1/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernet_dma_1/axi_resetn] +set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] +set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn] +set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/ui_clk] +set sys_100m_clk_source [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_clock_1/clk_out1] [get_bd_pins axi_interconnect_1/ACLK] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_reset_1/slowest_sync_clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins microblaze_1/Clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins mb_debug/S_AXI_ACLK] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb/LMB_Clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb/LMB_Clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb_cntlr/LMB_Clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb_cntlr/LMB_Clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_1/s_axi_lite_clk] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_uart_1/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_timer_1/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_intc_1/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_1/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_2/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_iic_1/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_1/axis_clk] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/m_axi_sg_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/m_axi_mm2s_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/m_axi_s2mm_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/s_axi_lite_aclk] +connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source +connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source +connect_bd_net -net sys_100m_clk $sys_100m_clk_source +connect_bd_net -net sys_200m_clk $sys_200m_clk_source -connect_bd_net -net proc_sys_clk_1_200mhz [get_bd_pins proc_sys_clock_1/clk_out2] [get_bd_pins axi_interconnect_2/ACLK] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_200m_resetn_source +connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_200m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source -connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins axi_ddr_cntrl_1/ui_clk] -connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins proc_sys_clock_1/clk_in1] -connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins axi_ethernet_1/ref_clk] [get_bd_pins axi_ddr_cntrl_1/ui_clk] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ddr_cntrl/aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet/s_axi_lite_resetn] [get_bd_pins sys_rstgen/peripheral_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_uart/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_timer/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_intc/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet_dma/axi_resetn] + +connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb/Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_uart/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_timer/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_intc/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/axis_clk] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/ref_clk] $sys_100m_clk_source # defaults (interconnect - processor) -connect_bd_intf_net -intf_net axi_interconnect_1_s00 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DP] -connect_bd_intf_net -intf_net axi_interconnect_1_m00 [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins mb_debug/S_AXI] -connect_bd_intf_net -intf_net axi_interconnect_1_m01 [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_ethernet_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m02 [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_uart_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m03 [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_timer_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m04 [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_intc_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m05 [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_gpio_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m06 [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_gpio_2/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m07 [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_iic_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m13 [get_bd_intf_pins axi_interconnect_1/M13_AXI] [get_bd_intf_pins axi_ethernet_dma_1/S_AXI_LITE] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M13_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M13_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] +connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_uart/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_timer/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_intc/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m06 [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_iic_main/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m13 [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ethernet_dma/S_AXI_LITE] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source # defaults (interconnect - memory) -connect_bd_intf_net -intf_net axi_interconnect_2_m00 [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl_1/S_AXI] -connect_bd_intf_net -intf_net axi_interconnect_2_s00 [get_bd_intf_pins axi_interconnect_2/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DC] -connect_bd_intf_net -intf_net axi_interconnect_2_s01 [get_bd_intf_pins axi_interconnect_2/S01_AXI] [get_bd_intf_pins microblaze_1/M_AXI_IC] -connect_bd_intf_net -intf_net axi_interconnect_2_s05 [get_bd_intf_pins axi_interconnect_2/S05_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_SG] -connect_bd_intf_net -intf_net axi_interconnect_2_s06 [get_bd_intf_pins axi_interconnect_2/S06_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_MM2S] -connect_bd_intf_net -intf_net axi_interconnect_2_s07 [get_bd_intf_pins axi_interconnect_2/S07_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_S2MM] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S05_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S06_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S07_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] +connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/S_AXI] +connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC] +connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC] +connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG] +connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S] +connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM] +connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_200m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_200m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_100m_clk_source # ethernet & ethernet dma -connect_bd_net -net axi_ethernet_dma_1_txd_rstn [get_bd_pins axi_ethernet_1/axi_txd_arstn] [get_bd_pins axi_ethernet_dma_1/mm2s_prmry_reset_out_n] -connect_bd_net -net axi_ethernet_dma_1_txc_rstn [get_bd_pins axi_ethernet_1/axi_txc_arstn] [get_bd_pins axi_ethernet_dma_1/mm2s_cntrl_reset_out_n] -connect_bd_net -net axi_ethernet_dma_1_rxd_rstn [get_bd_pins axi_ethernet_1/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma_1/s2mm_prmry_reset_out_n] -connect_bd_net -net axi_ethernet_dma_1_rxs_rstn [get_bd_pins axi_ethernet_1/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma_1/s2mm_sts_reset_out_n] +connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n] +connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n] +connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n] +connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n] -connect_bd_intf_net -intf_net axi_ethernet_dma_1_txd [get_bd_intf_pins axi_ethernet_1/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma_1/M_AXIS_MM2S] -connect_bd_intf_net -intf_net axi_ethernet_dma_1_txc [get_bd_intf_pins axi_ethernet_1/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma_1/M_AXIS_CNTRL] -connect_bd_intf_net -intf_net axi_ethernet_dma_1_rxd [get_bd_intf_pins axi_ethernet_1/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma_1/S_AXIS_S2MM] -connect_bd_intf_net -intf_net axi_ethernet_dma_1_rxs [get_bd_intf_pins axi_ethernet_1/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma_1/S_AXIS_STS] +connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S] +connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL] +connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM] +connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS] # defaults (interrupts) -connect_bd_net -net concat_intc_1_intr_00 [get_bd_pins concat_intc_1/In0] [get_bd_pins axi_timer_1/interrupt] -connect_bd_net -net concat_intc_1_intr_01 [get_bd_pins concat_intc_1/In1] [get_bd_pins axi_ethernet_1/interrupt] -connect_bd_net -net concat_intc_1_intr_02 [get_bd_pins concat_intc_1/In2] [get_bd_pins axi_uart_1/interrupt] -connect_bd_net -net concat_intc_1_intr_03 [get_bd_pins concat_intc_1/In3] [get_bd_pins axi_gpio_1/ip2intc_irpt] -connect_bd_net -net concat_intc_1_intr_04 [get_bd_pins concat_intc_1/In4] [get_bd_pins axi_gpio_2/ip2intc_irpt] -connect_bd_net -net concat_intc_1_intr_05 [get_bd_pins concat_intc_1/In5] [get_bd_pins axi_iic_1/iic2intc_irpt] -connect_bd_net -net concat_intc_1_intr_08 [get_bd_pins concat_intc_1/In8] [get_bd_pins axi_ethernet_dma_1/mm2s_introut] -connect_bd_net -net concat_intc_1_intr_09 [get_bd_pins concat_intc_1/In9] [get_bd_pins axi_ethernet_dma_1/s2mm_introut] +connect_bd_net -net sys_concat_intc_intr_00 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt] +connect_bd_net -net sys_concat_intc_intr_01 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/interrupt] +connect_bd_net -net sys_concat_intc_intr_02 [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_uart/interrupt] +connect_bd_net -net sys_concat_intc_intr_03 [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] +connect_bd_net -net sys_concat_intc_intr_04 [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] +connect_bd_net -net sys_concat_intc_intr_05 [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_iic_main/iic2intc_irpt] +connect_bd_net -net sys_concat_intc_intr_08 [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_ethernet_dma/mm2s_introut] +connect_bd_net -net sys_concat_intc_intr_09 [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_ethernet_dma/s2mm_introut] # defaults (external interface) -connect_bd_net -net proc_const_vcc_1_vcc [get_bd_pins proc_const_vcc_1/const] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet_1/signal_detect] -connect_bd_net -net sys_rst_s [get_bd_ports sys_rst] -connect_bd_net -net sys_rst_s [get_bd_pins proc_sys_reset_1/ext_reset_in] -connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl_1/sys_rst] +connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/const] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet/signal_detect] +connect_bd_net -net sys_rst_s [get_bd_ports sys_rst] +connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in] +connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst] -connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl_1/sys_clk_p] -connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl_1/sys_clk_n] +connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/sys_clk_p] +connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/sys_clk_n] -connect_bd_intf_net -intf_net axi_ddr_cntrl_1_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl_1/DDR3] -connect_bd_net -net axi_ethernet_1_phy_rstn [get_bd_ports phy_rstn] [get_bd_pins axi_ethernet_1/phy_rst_n] -connect_bd_intf_net -intf_net axi_ethernet_1_mgt_clk [get_bd_intf_ports mgt_clk] [get_bd_intf_pins axi_ethernet_1/mgt_clk] -connect_bd_intf_net -intf_net axi_ethernet_1_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet_1/sgmii] -connect_bd_intf_net -intf_net axi_ethernet_1_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet_1/mdio] +connect_bd_intf_net -intf_net axi_ddr_cntrl_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl/DDR3] +connect_bd_net -net axi_ethernet_phy_rstn [get_bd_ports phy_rstn] [get_bd_pins axi_ethernet/phy_rst_n] +connect_bd_intf_net -intf_net axi_ethernet_mgt_clk [get_bd_intf_ports mgt_clk] [get_bd_intf_pins axi_ethernet/mgt_clk] +connect_bd_intf_net -intf_net axi_ethernet_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet/sgmii] +connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio] -connect_bd_net -net axi_uart_1_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart_1/rx] -connect_bd_net -net axi_uart_1_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart_1/tx] +connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx] +connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx] -connect_bd_intf_net -intf_net axi_gpio_1_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_1/gpio] -connect_bd_intf_net -intf_net axi_gpio_2_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_2/gpio] -connect_bd_intf_net -intf_net axi_gpio_2_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_2/gpio2] +connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio] +connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] +connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] -connect_bd_net -net axi_iic_1_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_1/gpo] -connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_1/iic] +connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo] +connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] # hdmi peripherals -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_dma/axi_resetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_core/s_axi_aresetn] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/drp_clk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/s_axi_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] -connect_bd_net -net proc_sys_clk_1_200mhz [get_bd_pins axi_hdmi_clkgen/clk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] +connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk] -connect_bd_intf_net -intf_net axi_interconnect_1_m08 [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m09 [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE] -connect_bd_intf_net -intf_net axi_interconnect_1_m10 [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m09 [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m10 [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source -connect_bd_intf_net -intf_net axi_interconnect_2_s02 [get_bd_intf_pins axi_interconnect_2/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] +connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source -connect_bd_net -net concat_intc_1_intr_06 [get_bd_pins concat_intc_1/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_concat_intc_intr_06 [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut] connect_bd_net -net axi_hdmi_core_hdmi_out_clk [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk] connect_bd_net -net axi_hdmi_core_hdmi_hsync [get_bd_ports hdmi_hsync] [get_bd_pins axi_hdmi_core/hdmi_36_hsync] @@ -397,68 +396,68 @@ connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_f # spdif audio -connect_bd_intf_net -intf_net axi_interconnect_1_m11 [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m12 [get_bd_intf_pins axi_interconnect_1/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M12_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN] -connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_dma/axi_resetn] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M12_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m11 [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m12 [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] -connect_bd_intf_net -intf_net axi_interconnect_2_s03 [get_bd_intf_pins axi_interconnect_2/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG] -connect_bd_intf_net -intf_net axi_interconnect_2_s04 [get_bd_intf_pins axi_interconnect_2/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] -connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] +connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG] +connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid] connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata] connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast] connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready] -connect_bd_net -net concat_intc_1_intr_07 [get_bd_pins concat_intc_1/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] - -connect_bd_net -net proc_sys_clk_1_200mhz [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_concat_intc_intr_07 [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] + +connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] $sys_200m_clk_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] # address mapping -create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr -create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs mb_debug/S_AXI/Reg] SEG_data_mb_debug -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_data_ddr_cntrl_1 -create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ethernet_1/eth_buf/S_AXI/REG] SEG_data_ethernetlite_1 -create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_gpio_1/s_axi/Reg] SEG_data_gpio_1 -create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_gpio_2/s_axi/Reg] SEG_data_gpio_2 -create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_iic_1/s_axi/Reg] SEG_data_iic_1 -create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_intc_1/s_axi/Reg] SEG_data_intc_1 -create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_timer_1/s_axi/Reg] SEG_data_timer_1 -create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_uart_1/s_axi/Reg] SEG_data_uart_1 -create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ethernet_dma_1/S_AXI_LITE/Reg] SEG_data_ethernet_dma_1 +create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr +create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_data_ddr_cntrl_1 +create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet/eth_buf/S_AXI/REG] SEG_data_ethernetlite_1 +create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg] SEG_data_gpio_1 +create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg] SEG_data_gpio_2 +create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_1 +create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_intc/s_axi/Reg] SEG_data_intc_1 +create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_timer/s_axi/Reg] SEG_data_timer_1 +create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_uart/s_axi/Reg] SEG_data_uart_1 +create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet_dma/S_AXI_LITE/Reg] SEG_data_ethernet_dma_1 -create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen -create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma -create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core +create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen +create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma +create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core -create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core -create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma +create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core +create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma -create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Instruction] [get_bd_addr_segs ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Instruction] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_instr_ddr_cntrl_1 +create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_instr_ddr_cntrl_1 -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_mem_ddr_cntrl_1 -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1 -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1 +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_SG] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1 -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1 -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1 +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl diff --git a/projects/common/vc707/vc707_system_mig.prj b/projects/common/vc707/vc707_system_mig.prj index 829ed4d81..f49a2e30b 100644 --- a/projects/common/vc707/vc707_system_mig.prj +++ b/projects/common/vc707/vc707_system_mig.prj @@ -19,12 +19,12 @@ 0 DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6 - 2500 - 1.8V + 1250 + 2.0V 4:1 200 - 0 - 1.000 + 1 + 8.000 1 1 1 @@ -40,122 +40,123 @@ 10 3 1.5V + 1073741824 ROW_BANK_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -170,7 +171,7 @@ 8 - Fixed Sequential - 6 + 11 Normal No Slow Exit @@ -184,16 +185,16 @@ Enabled Output Buffer Enabled Full Array - 5 + 8 Enabled Normal Dynamic ODT off AXI RD_PRI_REG - 32 + 30 512 - 3 + 1 0 From 77ed085641981123f486d493e64951942bed15ad Mon Sep 17 00:00:00 2001 From: rejeesh kutty Date: Mon, 10 Mar 2014 16:41:22 -0400 Subject: [PATCH 4/4] Update README.md --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 39f4fa6e5..a393447f3 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,6 @@ hdl === -HDL libraries and projects +Analog Devices HDL libraries and projects + +http://wiki.analog.com/resources/fpga/docs/hdl/github