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axi_ad9434: Fix input data rate

main
AndreiGrozav 2017-05-04 16:38:21 +03:00
parent db459d96e9
commit e2ef470150
1 changed files with 6 additions and 3 deletions
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9
library/axi_ad9434/axi_ad9434_if.v
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@ -152,7 +152,8 @@ module axi_ad9434_if (
.IODELAY_CTRL(0), .IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
.DATA_WIDTH(12)) .DATA_WIDTH(12),
.SERDES_FACTOR(4))
i_adc_data ( i_adc_data (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
@ -184,7 +185,8 @@ module axi_ad9434_if (
.IODELAY_CTRL(1), .IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
.DATA_WIDTH(1)) .DATA_WIDTH(1),
.SERDES_FACTOR(4))
i_adc_or ( i_adc_or (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
@ -217,7 +219,8 @@ module axi_ad9434_if (
.MMCM_VCO_DIV (6), .MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12), .MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2), .MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8)) .MMCM_CLK1_DIV (8),
.SERDES_FACTOR(4))
i_serdes_clk ( i_serdes_clk (
.rst (mmcm_rst), .rst (mmcm_rst),
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),