From e2f4a4c5cf9a1224c34326dbbc7f98add094e7b5 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 10 Jun 2015 13:40:55 -0400 Subject: [PATCH] library: make preset registered for timing paths --- library/axi_ad9144/axi_ad9144_ip.tcl | 4 +-- library/axi_ad9680/axi_ad9680_constr.xdc | 44 ------------------------ library/axi_ad9680/axi_ad9680_ip.tcl | 4 +-- library/axi_jesd_gt/axi_jesd_gt_ip.tcl | 4 +-- library/common/ad_axi_ip_constr.sdc | 3 +- library/common/ad_axi_ip_constr.xdc | 13 +++++++ library/common/up_adc_common.v | 14 ++++---- library/common/up_axis_dma_rx.v | 9 ++--- library/common/up_axis_dma_tx.v | 9 ++--- library/common/up_clkgen.v | 7 ++-- library/common/up_dac_common.v | 14 ++++---- library/common/up_hdmi_rx.v | 7 ++-- library/common/up_hdmi_tx.v | 9 ++--- 13 files changed, 59 insertions(+), 82 deletions(-) create mode 100644 library/common/ad_axi_ip_constr.xdc diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl index d20188ac3..d4f3428a7 100644 --- a/library/axi_ad9144/axi_ad9144_ip.tcl +++ b/library/axi_ad9144/axi_ad9144_ip.tcl @@ -20,12 +20,12 @@ adi_ip_files axi_ad9144 [list \ "axi_ad9144_core.v" \ "axi_ad9144_if.v" \ "axi_ad9144.v" \ - "axi_ad9144_constr.xdc" ] + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] adi_ip_properties axi_ad9144 adi_ip_constraints axi_ad9144 [list \ - "axi_ad9144_constr.xdc" ] + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] diff --git a/library/axi_ad9680/axi_ad9680_constr.xdc b/library/axi_ad9680/axi_ad9680_constr.xdc index d7f6c300c..e69de29bb 100644 --- a/library/axi_ad9680/axi_ad9680_constr.xdc +++ b/library/axi_ad9680/axi_ad9680_constr.xdc @@ -1,44 +0,0 @@ -set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] -set ad9680_clk [get_clocks -of_objects [get_ports rx_clk]] - -set_property ASYNC_REG TRUE \ - [get_cells -hier *toggle_m1_reg*] \ - [get_cells -hier *toggle_m2_reg*] \ - [get_cells -hier *state_m1_reg*] \ - [get_cells -hier *state_m2_reg*] - -set_false_path \ - -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $ad9680_clk] - -set_false_path \ - -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $up_clk] - -set_false_path \ - -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $up_clk] - -set_false_path \ - -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl index 299e53932..a6ffe2555 100644 --- a/library/axi_ad9680/axi_ad9680_ip.tcl +++ b/library/axi_ad9680/axi_ad9680_ip.tcl @@ -18,12 +18,12 @@ adi_ip_files axi_ad9680 [list \ "axi_ad9680_channel.v" \ "axi_ad9680_if.v" \ "axi_ad9680.v" \ - "axi_ad9680_constr.xdc" ] + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] adi_ip_properties axi_ad9680 adi_ip_constraints axi_ad9680 [list \ - "axi_ad9680_constr.xdc" ] + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl index 0ece35965..0de2fccba 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl @@ -13,12 +13,12 @@ adi_ip_files axi_jesd_gt [list \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_gt.v" \ "axi_jesd_gt.v" \ - "axi_jesd_gt_constr.xdc" ] + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] adi_ip_properties axi_jesd_gt adi_ip_constraints axi_jesd_gt [list \ - "axi_jesd_gt_constr.xdc" ] + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -of_objects [ipx::get_bus_interfaces axi_signal_clock \ diff --git a/library/common/ad_axi_ip_constr.sdc b/library/common/ad_axi_ip_constr.sdc index 4ca491938..d2fae5ae9 100644 --- a/library/common/ad_axi_ip_constr.sdc +++ b/library/common/ad_axi_ip_constr.sdc @@ -5,8 +5,7 @@ set_false_path -from [get_registers *up_count_toggle*] -to [get_registers *d_co set_false_path -from [get_registers *d_xfer_toggle*] -to [get_registers *up_xfer_state*] set_false_path -from [get_registers *d_xfer_toggle*] -to [get_registers *up_xfer_toggle*] set_false_path -from [get_registers *d_count_toggle*] -to [get_registers *up_count_toggle*] -set_false_path -to [get_registers *rst_p*] -set_false_path -to [get_registers *rst*] +set_false_path -from [get_registers *preset*] -to [get_registers *rst*] set_max_delay -from [get_registers *up_xfer_data*] -to [get_registers *d_data_cntrl*] 8.0 set_max_delay -from [get_registers *d_xfer_data*] -to [get_registers *up_data_status*] 20.0 diff --git a/library/common/ad_axi_ip_constr.xdc b/library/common/ad_axi_ip_constr.xdc new file mode 100644 index 000000000..1f527ac7d --- /dev/null +++ b/library/common/ad_axi_ip_constr.xdc @@ -0,0 +1,13 @@ + +set_false_path -from [get_cells -hier *up_xfer_toggle* -filter {primitive_subgroup == flop}] -to [get_cells -hier *d_xfer_state* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *up_xfer_toggle* -filter {primitive_subgroup == flop}] -to [get_cells -hier *d_xfer_toggle* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *up_count_toggle* -filter {primitive_subgroup == flop}] -to [get_cells -hier *d_count_toggle* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *d_xfer_toggle* -filter {primitive_subgroup == flop}] -to [get_cells -hier *up_xfer_state* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *d_xfer_toggle* -filter {primitive_subgroup == flop}] -to [get_cells -hier *up_xfer_toggle* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *d_count_toggle* -filter {primitive_subgroup == flop}] -to [get_cells -hier *up_count_toggle* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *preset* -filter {primitive_subgroup == flop}] -to [get_cells -hier *rst* -filter {primitive_subgroup == flop}] + +set_max_delay -from [get_cells -hier *up_xfer_data* -filter {primitive_subgroup == flop}] -to [get_cells -hier *d_data_cntrl* -filter {primitive_subgroup == flop}] 8.0 +set_max_delay -from [get_cells -hier *d_xfer_data* -filter {primitive_subgroup == flop}] -to [get_cells -hier *up_data_status* -filter {primitive_subgroup == flop}] 20.0 +set_max_delay -from [get_cells -hier *d_count_hold* -filter {primitive_subgroup == flop}] -to [get_cells -hier *up_d_count* -filter {primitive_subgroup == flop}] 20.0 + diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index ef00ab623..3c9326a68 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -156,6 +156,8 @@ module up_adc_common ( // internal registers + reg up_preset = 'd0; + reg up_mmcm_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0; @@ -183,8 +185,6 @@ module up_adc_common ( wire up_wreq_s; wire up_rreq_s; - wire up_preset_s; - wire up_mmcm_preset_s; wire up_status_s; wire up_sync_status_s; wire up_status_ovf_s; @@ -196,13 +196,13 @@ module up_adc_common ( assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; - assign up_mmcm_preset_s = ~up_mmcm_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_preset <= 1'd1; + up_mmcm_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_mmcm_resetn <= 'd0; @@ -223,6 +223,8 @@ module up_adc_common ( up_adc_gpio_out <= 'd0; up_adc_start_code <= 'd0; end else begin + up_preset <= 1'd0; + up_mmcm_preset <= ~up_mmcm_resetn; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; @@ -322,8 +324,8 @@ module up_adc_common ( // resets - ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst)); - ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst)); + ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst)); + ad_rst i_adc_rst_reg (.preset(up_preset), .clk(adc_clk), .rst(adc_rst)); // adc control & status diff --git a/library/common/up_axis_dma_rx.v b/library/common/up_axis_dma_rx.v index 4ecb82e09..36f39f066 100644 --- a/library/common/up_axis_dma_rx.v +++ b/library/common/up_axis_dma_rx.v @@ -108,6 +108,7 @@ module up_axis_dma_rx ( // internal registers + reg up_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; @@ -126,7 +127,6 @@ module up_axis_dma_rx ( wire up_wreq_s; wire up_rreq_s; - wire up_preset_s; wire up_dma_ovf_s; wire up_dma_unf_s; wire up_dma_status_s; @@ -135,12 +135,12 @@ module up_axis_dma_rx ( assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_resetn <= 'd0; @@ -150,6 +150,7 @@ module up_axis_dma_rx ( up_dma_ovf <= 'd0; up_dma_unf <= 'd0; end else begin + up_preset <= 1'd0; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; @@ -205,8 +206,8 @@ module up_axis_dma_rx ( // resets - ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst)); - ad_rst i_dma_rst_reg (.preset(up_preset_s), .clk(dma_clk), .rst(dma_rst)); + ad_rst i_adc_rst_reg (.preset(up_preset), .clk(adc_clk), .rst(adc_rst)); + ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst)); // dma control & status diff --git a/library/common/up_axis_dma_tx.v b/library/common/up_axis_dma_tx.v index 8f963c149..060eafd2a 100644 --- a/library/common/up_axis_dma_tx.v +++ b/library/common/up_axis_dma_tx.v @@ -100,6 +100,7 @@ module up_axis_dma_tx ( // internal registers + reg up_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; @@ -113,7 +114,6 @@ module up_axis_dma_tx ( wire up_wreq_s; wire up_rreq_s; - wire up_preset_s; wire up_dma_ovf_s; wire up_dma_unf_s; @@ -121,12 +121,12 @@ module up_axis_dma_tx ( assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_resetn <= 'd0; @@ -134,6 +134,7 @@ module up_axis_dma_tx ( up_dma_ovf <= 'd0; up_dma_unf <= 'd0; end else begin + up_preset <= 1'd0; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; @@ -183,8 +184,8 @@ module up_axis_dma_tx ( // resets - ad_rst i_dac_rst_reg (.preset(up_preset_s), .clk(dac_clk), .rst(dac_rst)); - ad_rst i_dma_rst_reg (.preset(up_preset_s), .clk(dma_clk), .rst(dma_rst)); + ad_rst i_dac_rst_reg (.preset(up_preset), .clk(dac_clk), .rst(dac_rst)); + ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst)); // dma control & status diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v index ae7bbdc96..3f9252454 100644 --- a/library/common/up_clkgen.v +++ b/library/common/up_clkgen.v @@ -101,6 +101,7 @@ module up_clkgen ( // internal registers + reg up_mmcm_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0; @@ -119,18 +120,17 @@ module up_clkgen ( wire up_wreq_s; wire up_rreq_s; - wire up_mmcm_preset_s; // decode block select assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; - assign up_mmcm_preset_s = ~up_mmcm_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_mmcm_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_mmcm_resetn <= 'd0; @@ -143,6 +143,7 @@ module up_clkgen ( up_drp_wdata <= 'd0; up_drp_rdata_hold <= 'd0; end else begin + up_mmcm_preset <= ~up_mmcm_resetn; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; @@ -201,7 +202,7 @@ module up_clkgen ( // resets - ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst)); + ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst)); endmodule diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index 148dc1b80..141354d87 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -146,6 +146,8 @@ module up_dac_common ( // internal registers + reg up_preset = 'd0; + reg up_mmcm_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0; @@ -182,8 +184,6 @@ module up_dac_common ( wire up_wreq_s; wire up_rreq_s; - wire up_preset_s; - wire up_mmcm_preset_s; wire up_xfer_done_s; wire up_status_s; wire up_status_ovf_s; @@ -196,13 +196,13 @@ module up_dac_common ( assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; - assign up_mmcm_preset_s = ~up_mmcm_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_preset <= 1'd1; + up_mmcm_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_mmcm_resetn <= 'd0; @@ -226,6 +226,8 @@ module up_dac_common ( up_usr_chanmax <= 'd0; up_dac_gpio_out <= 'd0; end else begin + up_preset <= 1'd0; + up_mmcm_preset <= ~up_mmcm_resetn; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; @@ -334,8 +336,8 @@ module up_dac_common ( // resets - ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst)); - ad_rst i_dac_rst_reg (.preset(up_preset_s), .clk(dac_clk), .rst(dac_rst)); + ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst)); + ad_rst i_dac_rst_reg (.preset(up_preset), .clk(dac_clk), .rst(dac_rst)); // dac control & status diff --git a/library/common/up_hdmi_rx.v b/library/common/up_hdmi_rx.v index 4d2cc1fd5..1de9025d7 100644 --- a/library/common/up_hdmi_rx.v +++ b/library/common/up_hdmi_rx.v @@ -114,6 +114,7 @@ module up_hdmi_rx ( // internal registers + reg up_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; @@ -138,7 +139,6 @@ module up_hdmi_rx ( wire up_wreq_s; wire up_rreq_s; - wire up_preset_s; wire up_dma_ovf_s; wire up_dma_unf_s; wire up_vs_oos_s; @@ -153,12 +153,12 @@ module up_hdmi_rx ( assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_resetn <= 'd0; @@ -177,6 +177,7 @@ module up_hdmi_rx ( up_vs_count <= 'd0; up_hs_count <= 'd0; end else begin + up_preset <= 1'd0; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin up_scratch <= up_wdata; @@ -268,7 +269,7 @@ module up_hdmi_rx ( // resets ad_rst i_hdmi_rst_reg ( - .preset (up_preset_s), + .preset (up_preset), .clk (hdmi_clk), .rst (hdmi_rst)); diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index f7ef27411..9c47067b8 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -134,6 +134,7 @@ module up_hdmi_tx ( // internal registers + reg up_preset = 'd0; reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; @@ -162,7 +163,6 @@ module up_hdmi_tx ( wire up_wreq_s; wire up_rreq_s; - wire up_preset_s; wire up_hdmi_status_s; wire up_hdmi_tpm_oos_s; wire [31:0] up_hdmi_clk_count_s; @@ -174,12 +174,12 @@ module up_hdmi_tx ( assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0; assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; // processor write interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_preset <= 1'd1; up_wack <= 'd0; up_scratch <= 'd0; up_resetn <= 'd0; @@ -202,6 +202,7 @@ module up_hdmi_tx ( up_ve_max <= 'd0; up_ve_min <= 'd0; end else begin + up_preset <= 1'd0; up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin up_scratch <= up_wdata; @@ -302,8 +303,8 @@ module up_hdmi_tx ( // resets - ad_rst i_hdmi_rst_reg (.preset(up_preset_s), .clk(hdmi_clk), .rst(hdmi_rst)); - ad_rst i_vdma_rst_reg (.preset(up_preset_s), .clk(vdma_clk), .rst(vdma_rst)); + ad_rst i_hdmi_rst_reg (.preset(up_preset), .clk(hdmi_clk), .rst(hdmi_rst)); + ad_rst i_vdma_rst_reg (.preset(up_preset), .clk(vdma_clk), .rst(vdma_rst)); // hdmi control & status