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ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection

main
Adrian Costina 2015-04-30 12:11:46 +03:00
parent d623f77453
commit e332fa01c8
5 changed files with 5 additions and 5 deletions
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2
projects/ad6676evb/common/ad6676evb_bd.tcl
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@ -66,7 +66,7 @@ ad_connect ad6676_clk axi_ad6676_gt/rx_clk
ad_connect ad6676_clk axi_ad6676_core/rx_clk
ad_connect ad6676_clk axi_ad6676_jesd/rx_core_clk
ad_connect ad6676_clk axi_ad6676_dma/fifo_wr_clk
ad_connect axi_ad6676_gt/rx_rst axi_ad6676_jesd/rx_reset
ad_connect axi_ad6676_gt/rx_jesd_rst axi_ad6676_jesd/rx_reset
ad_connect axi_ad6676_gt/rx_sysref axi_ad6676_jesd/rx_sysref
ad_connect axi_ad6676_gt/tx_clk_g axi_ad6676_gt/tx_clk

2
projects/daq2/common/daq2_bd.tcl
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@ -165,7 +165,7 @@ ad_connect axi_daq2_gt/rx_clk_g adc_clk
ad_connect axi_daq2_gt/rx_clk_g axi_daq2_gt/rx_clk
ad_connect axi_daq2_gt/rx_clk_g axi_ad9680_core/rx_clk
ad_connect axi_daq2_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk
ad_connect axi_daq2_gt/rx_rst axi_ad9680_jesd/rx_reset
ad_connect axi_daq2_gt/rx_jesd_rst axi_ad9680_jesd/rx_reset
ad_connect axi_daq2_gt/rx_sysref axi_ad9680_jesd/rx_sysref
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk

2
projects/fmcadc2/common/fmcadc2_bd.tcl
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@ -53,7 +53,7 @@ ad_connect axi_ad9625_gt/tx_clk_g axi_ad9625_gt/tx_clk
ad_connect axi_ad9625_gt/rx_clk_g axi_ad9625_gt/rx_clk
ad_connect axi_ad9625_gt/rx_clk_g axi_ad9625_core/rx_clk
ad_connect axi_ad9625_gt/rx_clk_g axi_ad9625_jesd/rx_core_clk
ad_connect axi_ad9625_gt/rx_rst axi_ad9625_jesd/rx_reset
ad_connect axi_ad9625_gt/rx_jesd_rst axi_ad9625_jesd/rx_reset
ad_connect axi_ad9625_gt/rx_sysref axi_ad9625_jesd/rx_sysref
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk

2
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
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@ -112,7 +112,7 @@ ad_connect axi_ad9250_gt_rx_clk axi_ad9250_0_core/rx_clk
ad_connect axi_ad9250_gt_rx_clk axi_ad9250_1_core/rx_clk
ad_connect axi_ad9250_gt_rx_clk axi_ad9250_jesd/rx_core_clk
ad_connect axi_ad9250_gt_rx_clk adc_clk
ad_connect axi_ad9250_gt_rx_rst axi_ad9250_gt/rx_rst
ad_connect axi_ad9250_gt_rx_rst axi_ad9250_gt/rx_jesd_rst
ad_connect axi_ad9250_gt_rx_rst axi_ad9250_jesd/rx_reset
ad_connect axi_ad9250_gt_rx_sysref axi_ad9250_jesd/rx_sysref

2
projects/usdrx1/common/usdrx1_bd.tcl
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@ -125,7 +125,7 @@ ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_1/rx_clk
ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_2/rx_clk
ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_3/rx_clk
ad_connect axi_usdrx1_gt_rx_clk axi_usdrx1_jesd/rx_core_clk
ad_connect axi_usdrx1_gt/rx_rst axi_usdrx1_jesd/rx_reset
ad_connect axi_usdrx1_gt/rx_jesd_rst axi_usdrx1_jesd/rx_reset
ad_connect axi_usdrx1_gt/rx_sysref axi_usdrx1_jesd/rx_sysref
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk