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adrv9371x/a10gx- constraints/project updates

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Rejeesh Kutty 2017-06-06 12:22:31 -04:00
parent e9c49f667f
commit e34057c2b2
2 changed files with 2 additions and 3 deletions
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3
projects/adrv9371x/a10gx/system_constr.sdc
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@ -1,11 +1,10 @@
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]

2
projects/adrv9371x/a10gx/system_project.tcl
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@ -4,7 +4,7 @@ source ../../scripts/adi_project_alt.tcl
adi_project_altera adrv9371x_a10gx
source "../../common/a10gx/a10gx_system_assign.tcl"
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
# lane interface