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axi_dmac: Fix Vivado warnings 

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-03-18 20:58:56 +01:00
parent 29d590c951
commit e373b85954
8 changed files with 88 additions and 24 deletions
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6
library/axi_dmac/address_generator.v
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@ -45,7 +45,7 @@ module dmac_address_generator (
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] wait_id,
input [C_ID_WIDTH-1:0] request_id,
input sync_id,
input eot,
@ -116,7 +116,7 @@ always @(posedge clk) begin
addr_valid <= 1'b0;
if (eot)
req_ready <= 1'b1;
end else if (id != wait_id && enable) begin
end else if (id != request_id && enable) begin
addr_valid <= 1'b1;
end
end
@ -128,7 +128,7 @@ always @(posedge clk) begin
id <='h0;
end else begin
if ((addr_valid && addr_ready) ||
(sync_id && id != wait_id))
(sync_id && id != request_id))
id <= inc_id(id);
end
end

7
library/axi_dmac/dest_axi_mm.v
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@ -99,9 +99,6 @@ parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
wire [C_ID_WIDTH-1:0] data_id;
wire [C_ID_WIDTH-1:0] address_id;
reg [(C_DMA_DATA_WIDTH/8)-1:0] wstrb;
wire address_req_valid;
@ -147,7 +144,7 @@ dmac_address_generator #(
.pause(pause),
.id(address_id),
.wait_id(request_id),
.request_id(request_id),
.sync_id(sync_id),
.req_valid(address_req_valid),
@ -220,7 +217,7 @@ dmac_response_handler #(
.enabled(enabled),
.id(response_id),
.wait_id(data_id),
.request_id(data_id),
.sync_id(sync_id),
.eot(response_eot),

1
library/axi_dmac/dest_axi_stream.v
View File

@ -75,7 +75,6 @@ parameter C_BEATS_PER_BURST_WIDTH = 4;
assign sync_id_ret = sync_id;
wire data_enabled;
wire [C_ID_WIDTH-1:0] data_id;
wire _fifo_ready;
// We are not allowed to just de-assert valid, but if the streaming target does

4
library/axi_dmac/dest_fifo_inf.v
View File

@ -76,7 +76,6 @@ parameter C_BEATS_PER_BURST_WIDTH = 4;
assign sync_id_ret = sync_id;
wire data_enabled;
wire [C_ID_WIDTH-1:0] data_id;
wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
@ -129,7 +128,8 @@ dmac_data_mover # (
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout)
.m_axi_data(dout),
.m_axi_last()
);
dmac_response_generator # (

71
library/axi_dmac/request_arb.v
View File

@ -432,8 +432,26 @@ dmac_dest_mm_axi #(
.m_axi_bready(m_axi_bready)
);
end else if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
end else begin
assign m_axi_awvalid = 1'b0;
assign m_axi_awaddr = 'h00;
assign m_axi_awlen = 'h00;
assign m_axi_awsize = 'h00;
assign m_axi_awburst = 'h00;
assign m_axi_awprot = 'h00;
assign m_axi_awcache = 'h00;
assign m_axi_wvalid = 1'b0;
assign m_axi_wdata = 'h00;
assign m_axi_wstrb = 'h00;
assign m_axi_wlast = 1'b0;
assign m_axi_bready = 1'b0;
end
if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
assign dest_clk = m_axis_aclk;
@ -483,7 +501,14 @@ dmac_dest_axi_stream #(
.m_axis_data(m_axis_data)
);
end else /* if (C_DMA_TYPE_DEST == DMA_TYPE_FIFO) */ begin
end else begin
assign m_axis_valid = 1'b0;
assign m_axis_data = 'h00;
end
if (C_DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
assign dest_clk = fifo_rd_clk;
@ -534,6 +559,12 @@ dmac_dest_fifo_inf #(
.underflow(fifo_rd_underflow)
);
end else begin
assign fifo_rd_valid = 1'b0;
assign fifo_rd_dout = 'h0;
assign fifo_rd_underflow = 1'b0;
end endgenerate
generate if (C_DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
@ -558,6 +589,7 @@ dmac_src_mm_axi #(
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(m_src_axi_aresetn),
.pause(pause),
.enable(src_enable),
.enabled(src_enabled),
.sync_id(src_sync_id),
@ -599,7 +631,20 @@ dmac_src_mm_axi #(
.m_axi_rresp(m_axi_rresp)
);
end else if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
end else begin
assign m_axi_arvalid = 1'b0;
assign m_axi_araddr = 'h00;
assign m_axi_arlen = 'h00;
assign m_axi_arsize = 'h00;
assign m_axi_arburst = 'h00;
assign m_axi_arcache = 'h00;
assign m_axi_arprot = 'h00;
assign m_axi_rready = 1'b0;
end
if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
assign src_clk = s_axis_aclk;
@ -608,6 +653,10 @@ wire src_eot = eot_mem_src[src_response_id];
assign dbg_src_address_id = 'h00;
assign dbg_src_data_id = 'h00;
/* TODO */
assign src_response_valid = 1'b0;
assign src_response_resp = 2'b0;
dmac_src_axi_stream #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_S_AXIS_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
@ -641,7 +690,13 @@ dmac_src_axi_stream #(
.s_axis_user(s_axis_user)
);
end else /* if (C_DMA_TYPE_SRC == DMA_TYPE_FIFO) */ begin
end else begin
assign s_axis_ready = 1'b0;
end
if (C_DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
assign src_clk = fifo_wr_clk;
@ -650,6 +705,10 @@ wire src_eot = eot_mem_src[src_response_id];
assign dbg_src_address_id = 'h00;
assign dbg_src_data_id = 'h00;
/* TODO */
assign src_response_valid = 1'b0;
assign src_response_resp = 2'b0;
dmac_src_fifo_inf #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
@ -683,6 +742,10 @@ dmac_src_fifo_inf #(
.sync(fifo_wr_sync)
);
end else begin
assign fifo_wr_overflow = 1'b0;
end endgenerate
sync_bits #(

8
library/axi_dmac/response_handler.v
View File

@ -45,7 +45,7 @@ module dmac_response_handler (
input [1:0] bresp,
output reg [C_ID_WIDTH-1:0] id,
input [C_ID_WIDTH-1:0] wait_id,
input [C_ID_WIDTH-1:0] request_id,
input sync_id,
input enable,
@ -67,7 +67,7 @@ parameter C_ID_WIDTH = 3;
assign resp_resp = bresp;
assign resp_eot = eot;
wire active = id != wait_id && enabled;
wire active = id != request_id && enabled;
assign bready = active && resp_ready;
assign resp_valid = active && bvalid;
@ -79,7 +79,7 @@ always @(posedge clk) begin
end else begin
if (enable)
enabled <= 1'b1;
else if (wait_id == id)
else if (request_id == id)
enabled <= 1'b0;
end
end
@ -89,7 +89,7 @@ always @(posedge clk) begin
id <= 'h0;
end else begin
if ((bready && bvalid) ||
(sync_id && id != wait_id))
(sync_id && id != request_id))
id <= inc_id(id);
end
end

12
library/axi_dmac/src_axi_mm.v
View File

@ -89,8 +89,7 @@ parameter C_DMA_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BEATS_PER_BURST_WIDTH = 4;
wire [C_ID_WIDTH-1:0] data_id;
wire [C_ID_WIDTH-1:0] address_id;
`include "resp.h"
wire address_enabled;
@ -102,6 +101,9 @@ wire data_req_ready;
assign sync_id_ret = sync_id;
assign response_id = data_id;
assign response_valid = 1'b0;
assign response_resp = RESP_OKAY;
splitter #(
.C_NUM_M(2)
) i_req_splitter (
@ -130,10 +132,11 @@ dmac_address_generator #(
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.sync_id(sync_id),
.request_id(request_id),
.id(address_id),
.wait_id(request_id),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
@ -177,7 +180,8 @@ dmac_data_mover # (
.s_axi_data(m_axi_rdata),
.m_axi_valid(fifo_valid),
.m_axi_ready(fifo_ready),
.m_axi_data(fifo_data)
.m_axi_data(fifo_data),
.m_axi_last()
);
reg [1:0] rresp;

3
library/axi_dmac/src_fifo_inf.v
View File

@ -141,7 +141,8 @@ dmac_data_mover # (
.s_axi_data(buffer),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
.m_axi_data(fifo_data),
.m_axi_last()
);
endmodule