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util_tdd_sync: Update the synchronization interface 

Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
main
Istvan Csomortani 2016-02-10 12:43:16 +02:00
parent 1c3795ad02
commit e381d5170c
7 changed files with 42 additions and 73 deletions
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24
library/axi_ad9361/axi_ad9361.v
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@ -70,8 +70,7 @@ module axi_ad9361 (
// tdd sync (1s pulse)
tdd_sync,
tdd_sync_en,
tdd_terminal_type,
tdd_sync_cntr,
// delay clock
@ -194,8 +193,7 @@ module axi_ad9361 (
// tdd sync
input tdd_sync;
output tdd_sync_en;
output tdd_terminal_type;
output tdd_sync_cntr;
// delay clock
@ -415,17 +413,10 @@ module axi_ad9361 (
// additional flop to keep control and data synced
always @(posedge clk) begin
if(rst == 1) begin
adc_data_i0 <= 16'b0;
adc_data_q0 <= 16'b0;
adc_data_i1 <= 16'b0;
adc_data_q1 <= 16'b0;
end else begin
adc_data_i0 <= adc_data_i0_s;
adc_data_q0 <= adc_data_q0_s;
adc_data_i1 <= adc_data_i1_s;
adc_data_q1 <= adc_data_q1_s;
end
adc_data_i0 <= adc_data_i0_s;
adc_data_q0 <= adc_data_q0_s;
adc_data_i1 <= adc_data_i1_s;
adc_data_q1 <= adc_data_q1_s;
end
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
@ -451,8 +442,7 @@ module axi_ad9361 (
.tdd_enabled (tdd_mode_s),
.tdd_status (tdd_status_s),
.tdd_sync (tdd_sync),
.tdd_sync_en (tdd_sync_en),
.tdd_terminal_type (tdd_terminal_type),
.tdd_sync_cntr (tdd_sync_cntr),
.tx_valid_i0 (dac_valid_i0_s),
.tx_valid_q0 (dac_valid_q0_s),
.tx_valid_i1 (dac_valid_i1_s),

13
library/axi_ad9361/axi_ad9361_tdd.v
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@ -61,8 +61,7 @@ module axi_ad9361_tdd (
// sync signal
tdd_sync,
tdd_sync_en,
tdd_terminal_type,
tdd_sync_cntr,
// tx/rx data flow control
@ -116,8 +115,7 @@ module axi_ad9361_tdd (
input [ 7:0] tdd_status;
input tdd_sync;
output tdd_sync_en;
output tdd_terminal_type;
output tdd_sync_cntr;
// tx data flow control
@ -211,6 +209,9 @@ module axi_ad9361_tdd (
assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
assign tdd_enabled = tdd_enable_s;
assign tdd_sync_cntr = ~(tdd_enable_s & tdd_terminal_type_s);
// tx/rx data flow control
always @(posedge clk) begin
@ -241,8 +242,6 @@ module axi_ad9361_tdd (
end
end
assign tdd_enabled = tdd_enable_s;
assign tdd_terminal_type = ~tdd_terminal_type_s;
// instantiations
@ -259,7 +258,6 @@ module axi_ad9361_tdd (
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_terminal_type(tdd_terminal_type_s),
.tdd_sync_enable(tdd_sync_enable_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
@ -309,7 +307,6 @@ module axi_ad9361_tdd (
.tdd_rx_only(tdd_rx_only_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_sync (tdd_sync),
.tdd_sync_en (tdd_sync_en),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),

6
library/common/ad_tdd_control.v
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@ -76,7 +76,6 @@ module ad_tdd_control(
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_sync,
tdd_sync_en,
// TDD control signals
@ -130,7 +129,6 @@ module ad_tdd_control(
input [23:0] tdd_tx_dp_off_2;
input tdd_sync;
output tdd_sync_en;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
@ -183,8 +181,6 @@ module ad_tdd_control(
reg tdd_sync_d2 = 1'b0;
reg tdd_sync_d3 = 1'b0;
reg tdd_sync_en = 1'b0;
// internal signals
wire [23:0] tdd_vco_rx_on_1_s;
@ -217,12 +213,10 @@ module ad_tdd_control(
// synchronization of tdd_sync
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_sync_en <= 1'b0;
tdd_sync_d1 <= 1'b0;
tdd_sync_d2 <= 1'b0;
tdd_sync_d3 <= 1'b0;
end else begin
tdd_sync_en <= tdd_enable;
tdd_sync_d1 <= tdd_sync;
tdd_sync_d2 <= tdd_sync_d1;
tdd_sync_d3 <= tdd_sync_d2;

20
library/common/up_tdd_cntrl.v
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@ -55,7 +55,6 @@ module up_tdd_cntrl (
tdd_counter_init,
tdd_frame_length,
tdd_terminal_type,
tdd_sync_enable,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
@ -110,7 +109,6 @@ module up_tdd_cntrl (
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
output tdd_terminal_type;
output tdd_sync_enable;
output [23:0] tdd_vco_rx_on_1;
output [23:0] tdd_vco_rx_off_1;
output [23:0] tdd_vco_tx_on_1;
@ -161,7 +159,6 @@ module up_tdd_cntrl (
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
reg up_tdd_terminal_type = 1'h0;
reg up_tdd_sync_enable = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
@ -213,7 +210,6 @@ module up_tdd_cntrl (
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
up_tdd_terminal_type <= 1'h0;
up_tdd_sync_enable <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
@ -258,8 +254,7 @@ module up_tdd_cntrl (
up_tdd_frame_length <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_terminal_type <= up_wdata[1];
up_tdd_sync_enable <= up_wdata[0];
up_tdd_terminal_type <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
@ -346,8 +341,7 @@ module up_tdd_cntrl (
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
8'h14: up_rdata <= {30'h0, up_tdd_terminal_type,
up_tdd_sync_enable};
8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
@ -377,7 +371,7 @@ module up_tdd_cntrl (
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(16)) i_xfer_tdd_control (
up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
@ -387,9 +381,8 @@ module up_tdd_cntrl (
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
up_tdd_burst_count,
up_tdd_terminal_type,
up_tdd_sync_enable
}),
up_tdd_terminal_type
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
@ -400,8 +393,7 @@ module up_tdd_cntrl (
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count,
tdd_terminal_type,
tdd_sync_enable
tdd_terminal_type
}));
up_xfer_cntrl #(.DATA_WIDTH(528)) i_xfer_tdd_counter_values (

43
library/util_tdd_sync/util_tdd_sync.v
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@ -36,14 +36,20 @@
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
//
// Simple pulse generator for TDD control
// The module has two modes. In function of the state of sync_mode,
// the syncronization signal (sync_out) can get its value from an external
// source or from its internal generator.
//
`timescale 1ns/1ps
module util_tdd_sync (
clk,
rstn,
sync_en,
sync_type,
sync_mode,
sync_in,
sync_out
@ -52,21 +58,19 @@ module util_tdd_sync (
input clk;
input rstn;
input sync_en;
input sync_type;
input sync_mode;
input sync_in;
output sync_out;
parameter TDD_SYNC_PERIOD = 100000000;
reg sync_en_d1 = 1'b0;
reg sync_en_d2 = 1'b0;
reg sync_type_d1 = 1'b0;
reg sync_type_d2 = 1'b0;
reg sync_mode_d1 = 1'b0;
reg sync_mode_d2 = 1'b0;
reg sync_out = 1'b0;
wire sync_gen;
wire sync_internal;
wire sync_external;
// pulse generator
@ -76,36 +80,29 @@ module util_tdd_sync (
i_tdd_sync (
.clk (clk),
.rstn (rstn),
.sync (sync_gen)
.sync (sync_internal)
);
// synchronization logic
always @(posedge clk) begin
if(rstn == 1'b0) begin
sync_en_d1 <= 1'b0;
sync_en_d2 <= 1'b0;
sync_type_d1 <= 1'b0;
sync_type_d2 <= 1'b0;
sync_mode_d1 <= 1'b0;
sync_mode_d2 <= 1'b0;
end else begin
sync_en_d1 <= sync_en;
sync_en_d2 <= sync_en_d1;
sync_type_d1 <= sync_type;
sync_type_d2 <= sync_type_d1;
sync_mode_d1 <= sync_mode;
sync_mode_d2 <= sync_mode_d1;
end
end
// output logic
assign sync_external = sync_in;
always @(posedge clk) begin
if(rstn == 1'b0) begin
sync_out <= 1'b0;
end else begin
if(sync_en_d2 == 1'b1) begin
sync_out <= (sync_type_d2 == 1'b0) ? sync_gen : sync_in;
end else begin
sync_out <= 1'b0;
end
sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external;
end
end

3
library/util_tdd_sync/util_tdd_sync_constr.xdc
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@ -1,5 +1,4 @@
set_false_path -to [get_cells -hier -filter {NAME =~ *sync_en_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {NAME =~ *sync_type_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {NAME =~ *sync_mode_d1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {NAME =~ *sync_out_reg* && IS_SEQUENTIAL}]

6
projects/fmcomms2/common/fmcomms2_bd.tcl
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@ -64,6 +64,7 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
# connections
@ -143,9 +144,8 @@ ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
ad_connect util_ad9361_tdd_sync/sync_en axi_ad9361/tdd_sync_en
ad_connect util_ad9361_tdd_sync/sync_type axi_ad9361/tdd_terminal_type
ad_connect tdd_sync_t axi_ad9361/tdd_terminal_type
ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in