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fifo- monitor status signals

main
Rejeesh Kutty 2014-06-25 12:15:13 -04:00
parent 57bb3705f2
commit e38813fa9f
7 changed files with 111 additions and 157 deletions
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97
library/axi_fifo2s/axi_fifo2s.v
View File

@ -101,15 +101,10 @@ module axi_fifo2s (
axi_rdata,
axi_rready,
dbg_adc_clk,
dbg_adc_data,
dbg_axi_clk,
dbg_axi_data,
// transfer request
axi_xfer_req);
axi_xfer_req,
axi_xfer_status);
// parameters
@ -179,56 +174,58 @@ module axi_fifo2s (
input [DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// transfer request
// transfer request & status
input axi_xfer_req;
output [ 4:0] axi_xfer_status;
output dbg_adc_clk;
output [ 17:0] dbg_adc_data;
// internal registers
output dbg_axi_clk;
output [165:0] dbg_axi_data;
reg [ 4:0] axi_xfer_status = 'd0;
reg [ 4:0] axi_status_cnt = 'd0;
reg m_wovf_m = 'd0;
reg m_wovf = 'd0;
// internal signals
wire axi_rd_req_s;
wire [ 31:0] axi_rd_addr_s;
wire axi_rd_status_s;
wire axi_dwovf_s;
wire axi_dwunf_s;
wire axi_werror_s;
wire axi_rerror_s;
// debug
// status signals
assign dbg_adc_clk = m_clk;
assign dbg_adc_data[15: 0] = m_wdata[15:0];
assign dbg_adc_data[16:16] = m_wr;
assign dbg_adc_data[17:17] = m_wovf;
always @(posedge axi_clk) begin
if (axi_resetn == 1'b0) begin
axi_xfer_status <= 'd0;
axi_status_cnt <= 'd0;
end else begin
axi_xfer_status[4] <= axi_rerror_s;
axi_xfer_status[3] <= axi_werror_s;
axi_xfer_status[2] <= axi_dwunf_s;
axi_xfer_status[1] <= axi_dwovf_s;
axi_xfer_status[0] <= axi_mwovf;
if (axi_xfer_status == 0) begin
if (axi_status_cnt[4] == 1'b1) begin
axi_status_cnt <= axi_status_cnt + 1'b1;
end
end else begin
axi_status_cnt <= 5'd10;
end
end
end
assign dbg_axi_clk = axi_clk;
assign dbg_axi_data[ 15: 0] = axi_mwdata[15:0];
assign dbg_axi_data[ 16: 16] = axi_mwr;
assign dbg_axi_data[ 17: 17] = axi_mwovf;
assign dbg_axi_data[ 18: 18] = axi_mwpfull;
assign dbg_axi_data[ 19: 19] = axi_awvalid;
assign dbg_axi_data[ 51: 20] = axi_awaddr;
assign dbg_axi_data[ 52: 52] = axi_awready;
assign dbg_axi_data[ 53: 53] = axi_wvalid;
assign dbg_axi_data[ 69: 54] = axi_wdata[15:0];
assign dbg_axi_data[ 70: 70] = axi_wlast;
assign dbg_axi_data[ 71: 71] = axi_wready;
assign dbg_axi_data[ 72: 72] = axi_bvalid;
assign dbg_axi_data[ 74: 73] = axi_bresp;
assign dbg_axi_data[ 75: 75] = axi_bready;
assign dbg_axi_data[ 76: 76] = axi_arvalid;
assign dbg_axi_data[108: 77] = axi_araddr;
assign dbg_axi_data[109:109] = axi_arready;
assign dbg_axi_data[110:110] = axi_rvalid;
assign dbg_axi_data[112:111] = axi_rresp;
assign dbg_axi_data[113:113] = axi_rlast;
assign dbg_axi_data[129:114] = axi_rdata[15:0];
assign dbg_axi_data[130:130] = axi_rready;
assign dbg_axi_data[131:131] = axi_xfer_req;
assign dbg_axi_data[132:132] = axi_rd_req_s;
assign dbg_axi_data[164:133] = axi_rd_addr_s;
assign dbg_axi_data[165:165] = axi_rd_status_s;
always @(posedge m_clk) begin
if (m_rst == 1'b1) begin
m_wovf_m <= 'd0;
m_wovf <= 'd0;
end else begin
m_wovf_m <= axi_status_cnt[4];
m_wovf <= m_wovf_m;
end
end
// instantiations
@ -242,12 +239,10 @@ module axi_fifo2s (
.axi_xfer_req (axi_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_rd_status (axi_rd_status_s),
.m_rst (m_rst),
.m_clk (m_clk),
.m_wr (m_wr),
.m_wdata (m_wdata),
.m_wovf (m_wovf),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_awvalid (axi_awvalid),
@ -272,7 +267,10 @@ module axi_fifo2s (
.axi_bid (axi_bid),
.axi_bresp (axi_bresp),
.axi_buser (axi_buser),
.axi_bready (axi_bready));
.axi_bready (axi_bready),
.axi_dwovf (axi_dwovf_s),
.axi_dwunf (axi_dwunf_s),
.axi_werror (axi_werror_s));
axi_fifo2s_rd #(
.DATA_WIDTH (DATA_WIDTH),
@ -284,7 +282,6 @@ module axi_fifo2s (
.axi_xfer_req (axi_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_rd_status (axi_rd_status_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_arvalid (axi_arvalid),
@ -306,9 +303,9 @@ module axi_fifo2s (
.axi_rlast (axi_rlast),
.axi_rdata (axi_rdata),
.axi_rready (axi_rready),
.axi_rerror (axi_rerror_s),
.axi_mwr (axi_mwr),
.axi_mwdata (axi_mwdata),
.axi_mwovf (axi_mwovf),
.axi_mwpfull (axi_mwpfull));
endmodule

26
library/axi_fifo2s/axi_fifo2s_rd.v
View File

@ -46,7 +46,6 @@ module axi_fifo2s_rd (
axi_xfer_req,
axi_rd_req,
axi_rd_addr,
axi_rd_status,
// axi interface
@ -72,11 +71,14 @@ module axi_fifo2s_rd (
axi_rdata,
axi_rready,
// axi status
axi_rerror,
// fifo interface
axi_mwr,
axi_mwdata,
axi_mwovf,
axi_mwpfull);
// parameters
@ -95,7 +97,6 @@ module axi_fifo2s_rd (
input axi_xfer_req;
input axi_rd_req;
input [ 31:0] axi_rd_addr;
output axi_rd_status;
// axi interface
@ -121,11 +122,14 @@ module axi_fifo2s_rd (
input [DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// axi status
output axi_rerror;
// fifo interface
output axi_mwr;
output [DATA_WIDTH-1:0] axi_mwdata;
input axi_mwovf;
input axi_mwpfull;
// internal registers
@ -134,7 +138,6 @@ module axi_fifo2s_rd (
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_arerror = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_mwr = 'd0;
@ -142,7 +145,6 @@ module axi_fifo2s_rd (
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
reg axi_reset = 'd0;
reg axi_rd_status = 'd0;
// internal signals
@ -187,11 +189,9 @@ module axi_fifo2s_rd (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_arerror <= 'd0;
axi_arvalid <= 'd0;
axi_araddr <= 'd0;
end else begin
axi_arerror <= axi_rd & axi_arvalid;
if (axi_arvalid == 1'b1) begin
if (axi_arready == 1'b1) begin
axi_arvalid <= 1'b0;
@ -241,16 +241,6 @@ module axi_fifo2s_rd (
end
end
// combined status
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_status <= 'd0;
end else begin
axi_rd_status <= axi_mwovf | axi_arerror | axi_rerror;
end
end
endmodule
// ***************************************************************************

64
library/axi_fifo2s/axi_fifo2s_wr.v
View File

@ -46,7 +46,6 @@ module axi_fifo2s_wr (
axi_xfer_req,
axi_rd_req,
axi_rd_addr,
axi_rd_status,
// fifo interface
@ -54,7 +53,6 @@ module axi_fifo2s_wr (
m_clk,
m_wr,
m_wdata,
m_wovf,
// axi interface
@ -82,7 +80,13 @@ module axi_fifo2s_wr (
axi_bid,
axi_bresp,
axi_buser,
axi_bready);
axi_bready,
// axi status
axi_dwovf,
axi_dwunf,
axi_werror);
// parameters
@ -100,7 +104,6 @@ module axi_fifo2s_wr (
input axi_xfer_req;
output axi_rd_req;
output [ 31:0] axi_rd_addr;
input axi_rd_status;
// fifo interface
@ -108,7 +111,6 @@ module axi_fifo2s_wr (
input m_clk;
input m_wr;
input [DATA_WIDTH-1:0] m_wdata;
output m_wovf;
// axi interface
@ -138,6 +140,12 @@ module axi_fifo2s_wr (
input [ 3:0] axi_buser;
output axi_bready;
// axi status
output axi_dwovf;
output axi_dwunf;
output axi_werror;
// internal registers
reg [ 2:0] m_xfer_req_m = 'd0;
@ -150,8 +158,6 @@ module axi_fifo2s_wr (
reg m_rel_enable = 'd0;
reg m_rel_toggle = 'd0;
reg [ 5:0] m_rel_waddr = 'd0;
reg [ 2:0] m_status_m = 'd0;
reg m_wovf = 'd0;
reg [ 2:0] axi_rel_toggle_m = 'd0;
reg [ 5:0] axi_rel_waddr = 'd0;
reg [ 5:0] axi_waddr_m1 = 'd0;
@ -159,9 +165,9 @@ module axi_fifo2s_wr (
reg [ 5:0] axi_waddr = 'd0;
reg [ 5:0] axi_addr_diff = 'd0;
reg axi_almost_full = 'd0;
reg axi_unf = 'd0;
reg axi_dwunf = 'd0;
reg axi_almost_empty = 'd0;
reg axi_ovf = 'd0;
reg axi_dwovf = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg [ 5:0] axi_raddr = 'd0;
@ -172,13 +178,10 @@ module axi_fifo2s_wr (
reg [DATA_WIDTH-1:0] axi_rdata_d = 'd0;
reg axi_rd_req = 'd0;
reg [ 31:0] axi_rd_addr = 'd0;
reg axi_awerror = 'd0;
reg axi_awvalid = 'd0;
reg [ 31:0] axi_awaddr = 'd0;
reg axi_werror = 'd0;
reg axi_reset = 'd0;
reg [ 4:0] axi_status_cnt = 'd0;
reg axi_status = 'd0;
// internal signals
@ -188,7 +191,6 @@ module axi_fifo2s_wr (
wire axi_rd_s;
wire axi_req_s;
wire axi_rlast_s;
wire axi_status_s;
wire [DATA_WIDTH-1:0] axi_rdata_s;
// binary to grey conversion
@ -237,8 +239,6 @@ module axi_fifo2s_wr (
m_rel_enable <= 'd0;
m_rel_toggle <= 'd0;
m_rel_waddr <= 'd0;
m_status_m <= 'd0;
m_wovf <= 'd0;
end else begin
if ((m_wr == 1'b1) && (m_xfer_enable == 1'b1)) begin
m_waddr <= m_waddr + 1'b1;
@ -267,8 +267,6 @@ module axi_fifo2s_wr (
m_rel_toggle <= ~m_rel_toggle;
m_rel_waddr <= m_waddr;
end
m_status_m <= {m_status_m[1:0], axi_status};
m_wovf <= m_status_m[2];
end
end
@ -302,24 +300,24 @@ module axi_fifo2s_wr (
if (axi_resetn == 1'b0) begin
axi_addr_diff <= 'd0;
axi_almost_full <= 'd0;
axi_unf <= 'd0;
axi_dwunf <= 'd0;
axi_almost_empty <= 'd0;
axi_ovf <= 'd0;
axi_dwovf <= 'd0;
end else begin
axi_addr_diff <= axi_addr_diff_s[5:0];
if (axi_addr_diff > BUF_THRESHOLD_HI) begin
axi_almost_full <= 1'b1;
axi_unf <= axi_almost_empty;
axi_dwunf <= axi_almost_empty;
end else begin
axi_almost_full <= 1'b0;
axi_unf <= 1'b0;
axi_dwunf <= 1'b0;
end
if (axi_addr_diff < BUF_THRESHOLD_LO) begin
axi_almost_empty <= 1'b1;
axi_ovf <= axi_almost_full;
axi_dwovf <= axi_almost_full;
end else begin
axi_almost_empty <= 1'b0;
axi_ovf <= 1'b0;
axi_dwovf <= 1'b0;
end
end
end
@ -393,11 +391,9 @@ module axi_fifo2s_wr (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_awerror <= 'd0;
axi_awvalid <= 'd0;
axi_awaddr <= 'd0;
end else begin
axi_awerror <= axi_req_s & axi_awvalid;
if (axi_awvalid == 1'b1) begin
if (axi_awready == 1'b1) begin
axi_awvalid <= 1'b0;
@ -442,24 +438,6 @@ module axi_fifo2s_wr (
end
end
// combined status
assign axi_status_s = axi_ovf | axi_unf | axi_awerror | axi_werror | axi_rd_status;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_status_cnt <= 'd0;
axi_status <= 'd0;
end else begin
if (axi_status_s == 1'b1) begin
axi_status_cnt <= 5'h1f;
end else if (axi_status_cnt[4] == 1'b1) begin
axi_status_cnt <= axi_status_cnt + 1'b1;
end
axi_status <= axi_status_cnt[4];
end
end
// interface handler
ad_axis_inf_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (

2
library/util_rfifo/util_rfifo.v
View File

@ -126,7 +126,7 @@ module util_rfifo (
// read is non-destructive
assign fifo_rd = m_rd;
assign m_runf_s = s_runf | fifo_runf | fifo_rempty;
assign m_runf_s = s_runf | fifo_runf;
always @(posedge m_clk) begin
m_runf_m1 <= m_runf_s;

2
library/util_wfifo/util_wfifo.v
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@ -110,7 +110,7 @@ module util_wfifo (
// write is pass through
assign fifo_wr = m_wr;
assign m_wovf_s = s_wovf | fifo_wfull | fifo_wovf;
assign m_wovf_s = s_wovf | fifo_wovf;
genvar m;
generate

6
projects/ad9625_fmc/zc706/system_bd.tcl
View File

@ -28,6 +28,7 @@ connect_bd_net -net axi_ad9625_adc_dwr [get_bd_pins axi_ad9625_core/adc_dwr
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins axi_ad9625_core/adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins plddr3_fifo/axi_xfer_req]
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
@ -37,15 +38,18 @@ connect_bd_net -net axi_ad9625_adc_dsync [get_bd_pins axi_ad9625_core/adc_dsy
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_dma_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins ila_dma_mon/clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins ila_dma_mon/probe1]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2]
connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status]
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr

71
projects/common/zc706/zc706_system_plddr3.tcl
View File

@ -18,6 +18,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
create_bd_pin -dir I axi_xfer_req
create_bd_pin -dir O -from 4 -to 0 axi_xfer_status
create_bd_pin -dir I adc_rst
create_bd_pin -dir I -type clk adc_clk
@ -71,47 +72,45 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_intf_net -intf_net DDR3 [get_bd_intf_pins DDR3] [get_bd_intf_pins axi_ddr_cntrl/DDR3]
connect_bd_intf_net -intf_net axi_ddr3 [get_bd_intf_pins axi_ddr_cntrl/S_AXI] [get_bd_intf_pins axi_fifo2s/axi]
connect_bd_net -net adc_rst [get_bd_pins adc_rst]
connect_bd_net -net adc_rst [get_bd_pins axi_ddr_cntrl/sys_rst]
connect_bd_net -net adc_rst [get_bd_pins axi_fifo2s/m_rst]
connect_bd_net -net adc_clk [get_bd_pins adc_clk]
connect_bd_net -net adc_clk [get_bd_pins wfifo_ctl/m_clk]
connect_bd_net -net adc_clk [get_bd_pins wfifo_mem/wr_clk]
connect_bd_net -net adc_wr [get_bd_pins adc_wr] [get_bd_pins wfifo_ctl/m_wr]
connect_bd_net -net adc_wdata [get_bd_pins adc_wdata] [get_bd_pins wfifo_ctl/m_wdata]
connect_bd_net -net adc_wovf [get_bd_pins adc_wovf] [get_bd_pins wfifo_ctl/m_wovf]
connect_bd_net -net axi_xfer_req [get_bd_pins axi_xfer_req] [get_bd_pins axi_fifo2s/axi_xfer_req]
connect_bd_net -net dma_rstn [get_bd_pins dma_rstn]
connect_bd_net -net dma_rstn [get_bd_pins axi_ddr_cntrl/aresetn]
connect_bd_net -net dma_rstn [get_bd_pins axi_fifo2s/axi_resetn]
connect_bd_net -net dma_rstn [get_bd_pins rfifo_ctl/rstn]
connect_bd_net -net dma_rstn [get_bd_pins wfifo_ctl/rstn]
connect_bd_net -net axi_clk [get_bd_pins axi_ddr_cntrl/ui_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/axi_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/m_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_ctl/s_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_mem/rd_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_ctl/m_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_mem/wr_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/s_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/rd_clk]
connect_bd_net -net dma_clk [get_bd_pins dma_clk]
connect_bd_net -net adc_rst [get_bd_pins adc_rst]
connect_bd_net -net adc_rst [get_bd_pins axi_ddr_cntrl/sys_rst]
connect_bd_net -net adc_rst [get_bd_pins axi_fifo2s/m_rst]
connect_bd_net -net adc_clk [get_bd_pins adc_clk]
connect_bd_net -net adc_clk [get_bd_pins wfifo_ctl/m_clk]
connect_bd_net -net adc_clk [get_bd_pins wfifo_mem/wr_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_ddr_cntrl/ui_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/axi_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/m_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_ctl/s_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_mem/rd_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_ctl/m_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_mem/wr_clk]
connect_bd_net -net dma_rstn [get_bd_pins dma_rstn]
connect_bd_net -net dma_rstn [get_bd_pins axi_ddr_cntrl/aresetn]
connect_bd_net -net dma_rstn [get_bd_pins axi_fifo2s/axi_resetn]
connect_bd_net -net dma_rstn [get_bd_pins rfifo_ctl/rstn]
connect_bd_net -net dma_rstn [get_bd_pins wfifo_ctl/rstn]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/s_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/rd_clk]
connect_bd_net -net dma_clk [get_bd_pins dma_clk]
connect_bd_net -net adc_wr [get_bd_pins adc_wr] [get_bd_pins wfifo_ctl/m_wr]
connect_bd_net -net adc_wdata [get_bd_pins adc_wdata] [get_bd_pins wfifo_ctl/m_wdata]
connect_bd_net -net adc_wovf [get_bd_pins adc_wovf] [get_bd_pins wfifo_ctl/m_wovf]
connect_bd_net -net axi_xfer_req [get_bd_pins axi_xfer_req] [get_bd_pins axi_fifo2s/axi_xfer_req]
connect_bd_net -net axi_xfer_status [get_bd_pins axi_xfer_status] [get_bd_pins axi_fifo2s/axi_xfer_status]
connect_bd_net -net wfifo_ctl_fifo_rst [get_bd_pins wfifo_ctl/fifo_rst] [get_bd_pins wfifo_mem/rst]
connect_bd_net -net wfifo_ctl_fifo_wr [get_bd_pins wfifo_ctl/fifo_wr] [get_bd_pins wfifo_mem/wr_en]
connect_bd_net -net wfifo_ctl_fifo_wdata [get_bd_pins wfifo_ctl/fifo_wdata] [get_bd_pins wfifo_mem/din]
connect_bd_net -net wfifo_ctl_fifo_wfull [get_bd_pins wfifo_ctl/fifo_wfull] [get_bd_pins wfifo_mem/full]
connect_bd_net -net wfifo_ctl_fifo_wovf [get_bd_pins wfifo_ctl/fifo_wovf] [get_bd_pins wfifo_mem/overflow]
connect_bd_net -net dma_wr [get_bd_pins dma_wr] [get_bd_pins rfifo_ctl/s_wr]
connect_bd_net -net dma_wdata [get_bd_pins dma_wdata] [get_bd_pins rfifo_ctl/s_wdata]
connect_bd_net -net dma_wovf [get_bd_pins dma_wovf] [get_bd_pins rfifo_ctl/s_wovf]
connect_bd_net -net rfifo_ctl_fifo_rd [get_bd_pins rfifo_ctl/fifo_rd] [get_bd_pins rfifo_mem/rd_en]
connect_bd_net -net rfifo_ctl_fifo_rdata [get_bd_pins rfifo_ctl/fifo_rdata] [get_bd_pins rfifo_mem/dout]
connect_bd_net -net rfifo_ctl_fifo_rempty [get_bd_pins rfifo_ctl/fifo_rempty] [get_bd_pins rfifo_mem/empty]
connect_bd_net -net wfifo_ctl_fifo_rd [get_bd_pins wfifo_ctl/fifo_rd] [get_bd_pins wfifo_mem/rd_en]
connect_bd_net -net wfifo_ctl_fifo_rdata [get_bd_pins wfifo_ctl/fifo_rdata] [get_bd_pins wfifo_mem/dout]
connect_bd_net -net wfifo_ctl_fifo_rempty [get_bd_pins wfifo_ctl/fifo_rempty] [get_bd_pins wfifo_mem/empty]
@ -128,20 +127,6 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net axi_fifo2s_axi_mwovf [get_bd_pins axi_fifo2s/axi_mwovf] [get_bd_pins rfifo_ctl/m_wovf]
connect_bd_net -net axi_fifo2s_axi_mwpfull [get_bd_pins axi_fifo2s/axi_mwpfull] [get_bd_pins rfifo_mem/prog_full]
set ila_ddr_mon_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_ddr_mon_1]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ddr_mon_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {18}] $ila_ddr_mon_1
connect_bd_net [get_bd_pins axi_fifo2s/dbg_adc_clk] [get_bd_pins ila_ddr_mon_1/clk]
connect_bd_net [get_bd_pins axi_fifo2s/dbg_adc_data] [get_bd_pins ila_ddr_mon_1/probe0]
set ila_ddr_mon_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_ddr_mon_2]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ddr_mon_2
set_property -dict [list CONFIG.C_PROBE0_WIDTH {166}] $ila_ddr_mon_2
connect_bd_net [get_bd_pins axi_fifo2s/dbg_axi_clk] [get_bd_pins ila_ddr_mon_2/clk]
connect_bd_net [get_bd_pins axi_fifo2s/dbg_axi_data] [get_bd_pins ila_ddr_mon_2/probe0]
current_bd_instance $c_instance
}