From e3b834ea02fa0ecdbb3818a5b34ff0dafb4450a4 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 15 Apr 2015 17:16:41 +0200 Subject: [PATCH] axi_ad9361: Add CDC constraints Add proper constraints for all the CDC synchronizer paths to the axi_ad9361 core. Signed-off-by: Lars-Peter Clausen --- library/axi_ad9361/axi_ad9361_constr.xdc | 38 ++++++++++++++++++++++++ library/axi_ad9361/axi_ad9361_ip.tcl | 4 ++- 2 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 library/axi_ad9361/axi_ad9361_constr.xdc diff --git a/library/axi_ad9361/axi_ad9361_constr.xdc b/library/axi_ad9361/axi_ad9361_constr.xdc new file mode 100644 index 000000000..0284dd04a --- /dev/null +++ b/library/axi_ad9361/axi_ad9361_constr.xdc @@ -0,0 +1,38 @@ +set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set ad9361_clk [get_clocks -of_objects [get_ports clk]] + +set_false_path \ + -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay \ + -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $ad9361_clk] + +set_false_path \ + -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay \ + -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $up_clk] + +set_false_path \ + -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay \ + -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $up_clk] + +set_false_path \ + -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index bb400eb8e..d5c7350b3 100755 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -33,9 +33,11 @@ adi_ip_files axi_ad9361 [list \ "axi_ad9361_rx.v" \ "axi_ad9361_tx_channel.v" \ "axi_ad9361_tx.v" \ - "axi_ad9361.v" ] + "axi_ad9361.v" \ + "axi_ad9361_constr.xdc" ] adi_ip_properties axi_ad9361 +adi_ip_constraints axi_dmac "axi_ad9361_constr.xdc" "late" set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]