From e40311eee94a6a1a272416df6f2b88bd660beb13 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 29 Sep 2016 09:14:37 +0100 Subject: [PATCH] adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz --- projects/adrv9371x/common/adrv9371x_qsys.tcl | 22 +++++++++---------- projects/common/a10soc/a10soc_system_qsys.tcl | 12 +++++----- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl index dc98fb212..2913a0b8b 100644 --- a/projects/adrv9371x/common/adrv9371x_qsys.tcl +++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl @@ -451,7 +451,7 @@ set_instance_parameter_value rx_os_adcfifo {DMA_ADDRESS_WIDTH} {16} add_instance axi_adc_dma axi_dmac 1.0 set_instance_parameter_value axi_adc_dma {ID} {0} set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64} -set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128} set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24} set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0} set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1} @@ -468,7 +468,7 @@ set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16} add_instance axi_os_adc_dma axi_dmac 1.0 set_instance_parameter_value axi_os_adc_dma {ID} {0} set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64} -set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {128} set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24} set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0} set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1} @@ -617,9 +617,9 @@ if { $system_type=="nios" } { # SOC if { $system_type=="a10soc" } { - add_connection xcvr_pll.outclk1 axi_adc_dma.m_dest_axi_clock - add_connection xcvr_pll.outclk2 axi_os_adc_dma.m_dest_axi_clock - add_connection xcvr_pll.outclk0 axi_dac_dma.m_src_axi_clock + add_connection arria10_hps_0.h2f_user0_clock axi_adc_dma.m_dest_axi_clock + add_connection arria10_hps_0.h2f_user0_clock axi_os_adc_dma.m_dest_axi_clock + add_connection arria10_hps_0.h2f_user0_clock axi_dac_dma.m_src_axi_clock add_connection sys_rst.out_reset axi_adc_dma.m_dest_axi_reset add_connection sys_rst.out_reset axi_os_adc_dma.m_dest_axi_reset add_connection sys_rst.out_reset axi_dac_dma.m_src_axi_reset @@ -800,9 +800,9 @@ if { $system_type=="a10soc" } { add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.jesd204_tx_avs add_connection arria10_hps_0.h2f_lw_axi_master ad9371_gpio.s1 - add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram1_data - add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram1_data - add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram1_data + add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data + add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data + add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram0_data set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/ad9371_gpio.s1 baseAddress {0x00001000} set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x00010000} @@ -818,9 +818,9 @@ if { $system_type=="a10soc" } { set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_adc_dma.s_axi baseAddress {0x0090000} set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x000a0000} - set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000} - set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000} - set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram1_data baseAddress {0x0000} + set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000} + set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000} + set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000} } # interrupts diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl index c3e4e33e0..5df47d810 100755 --- a/projects/common/a10soc/a10soc_system_qsys.tcl +++ b/projects/common/a10soc/a10soc_system_qsys.tcl @@ -36,9 +36,9 @@ set_instance_parameter_value arria10_hps_0 {F2S_Width} {0} set_instance_parameter_value arria10_hps_0 {S2F_Width} {0} set_instance_parameter_value arria10_hps_0 {LWH2F_Enable} {1} set_instance_parameter_value arria10_hps_0 {RUN_INTERNAL_BUILD_CHECKS} {0} -set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {5} -set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {0} -set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {1} +set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {6} +set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {1} +set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {0} set_instance_parameter_value arria10_hps_0 {F2SDRAM2_ENABLED} {0} set_instance_parameter_value arria10_hps_0 {F2SDRAM_READY_LATENCY} {0} set_instance_parameter_value arria10_hps_0 {F2SDRAM2_DELAY} {4} @@ -100,8 +100,8 @@ set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2 set_instance_parameter_value arria10_hps_0 {MPU_CLK_VCCL} {0} set_instance_parameter_value arria10_hps_0 {USE_DEFAULT_MPU_CLK} {0} set_instance_parameter_value arria10_hps_0 {CUSTOM_MPU_CLK} {800} -set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {0} -set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {400} +set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {1} +set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {175} set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_Enable} {0} set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_FREQ} {400} set_instance_parameter_value arria10_hps_0 {HMC_PLL_REF_CLK} {800} @@ -1250,7 +1250,7 @@ add_connection sys_clk.clk gpio_i.clk clock add_connection sys_clk.clk gpio_o.clk clock add_connection sys_clk.clk sys_rst.clk clock -add_connection sys_clk.clk arria10_hps_0.f2sdram1_clock clock +add_connection arria10_hps_0.h2f_user0_clock arria10_hps_0.f2sdram0_clock clock add_connection emif_a10_hps_0.hps_emif_conduit_end arria10_hps_0.emif conduit set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPort {}