zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad9081_fmca_ebz: expose PLL selection as a parameter 

On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
main
Laszlo Nagy 2020-04-16 11:09:45 +01:00 committed by Laszlo Nagy
parent 70d139af7f
commit e433d3f808
2 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
View File

@ -131,10 +131,10 @@ ad_ip_instance jesd204_phy jesd204_phy_121 [list \
GT_Line_Rate $tx_rate \
GT_REFCLK_FREQ $ref_clk_rate \
DRPCLK_FREQ {50} \
C_PLL_SELECTION {1} \
C_PLL_SELECTION $ad_project_params(TX_PLL_SEL) \
RX_GT_Line_Rate $rx_rate \
RX_GT_REFCLK_FREQ $ref_clk_rate \
RX_PLL_SELECTION {1} \
RX_PLL_SELECTION $ad_project_params(RX_PLL_SEL) \
GT_Location {X0Y8} \
Tx_JesdVersion {1} \
Rx_JesdVersion {1} \
@ -150,10 +150,10 @@ ad_ip_instance jesd204_phy jesd204_phy_126 [list \
GT_Line_Rate $tx_rate \
GT_REFCLK_FREQ $ref_clk_rate \
DRPCLK_FREQ {50} \
C_PLL_SELECTION {1} \
C_PLL_SELECTION $ad_project_params(TX_PLL_SEL) \
RX_GT_Line_Rate $rx_rate \
RX_GT_REFCLK_FREQ $ref_clk_rate \
RX_PLL_SELECTION {1} \
RX_PLL_SELECTION $ad_project_params(RX_PLL_SEL) \
GT_Location {X0Y28} \
Tx_JesdVersion {1} \
Rx_JesdVersion {1} \

2
projects/ad9081_fmca_ebz/vcu118/system_project.tcl
View File

@ -18,7 +18,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9081_fmca_ebz_vcu118 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_RATE [get_env_param RX_RATE 10 ] \
RX_PLL_SEL [get_env_param RX_PLL_SEL 1 ] \
TX_RATE [get_env_param TX_RATE 10 ] \
TX_PLL_SEL [get_env_param TX_PLL_SEL 1 ] \
REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \