diff --git a/library/axi_dacfifo/axi_dacfifo.v b/library/axi_dacfifo/axi_dacfifo.v index e1af682ce..1b5b55bfa 100644 --- a/library/axi_dacfifo/axi_dacfifo.v +++ b/library/axi_dacfifo/axi_dacfifo.v @@ -201,10 +201,8 @@ module axi_dacfifo ( wire dac_rd_valid_s; wire [31:0] axi_last_addr_s; wire [31:0] dma_last_addr_s; - wire [(DAC_DATA_WIDTH-1):0] dac_data_s; wire dma_ready_s; - wire dma_valid_bp_s; wire [(AXI_DATA_WIDTH-1):0] dma_data_bp_s; wire dma_ready_bp_s; diff --git a/library/axi_dacfifo/axi_dacfifo_dac.v b/library/axi_dacfifo/axi_dacfifo_dac.v index d077b81cc..7c21f2bd1 100644 --- a/library/axi_dacfifo/axi_dacfifo_dac.v +++ b/library/axi_dacfifo/axi_dacfifo_dac.v @@ -71,6 +71,7 @@ module axi_dacfifo_dac ( (DAC_ADDRESS_WIDTH - 3); // BUF_THRESHOLD_LO will make sure that there are always at least two burst in the memmory + localparam AXI_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1); localparam AXI_BUF_THRESHOLD_HI = {(AXI_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1); localparam DAC_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1) * MEM_RATIO; diff --git a/library/axi_dacfifo/axi_dacfifo_rd.v b/library/axi_dacfifo/axi_dacfifo_rd.v index aef01ac36..263e2d845 100644 --- a/library/axi_dacfifo/axi_dacfifo_rd.v +++ b/library/axi_dacfifo/axi_dacfifo_rd.v @@ -92,28 +92,28 @@ module axi_dacfifo_rd ( // xfer last for read/write synchronization input axi_xfer_req; - input [ 31:0] axi_last_raddr; + input [31:0] axi_last_raddr; // axi interface input axi_clk; input axi_resetn; output axi_arvalid; - output [ 3:0] axi_arid; - output [ 1:0] axi_arburst; + output [ 3:0] axi_arid; + output [ 1:0] axi_arburst; output axi_arlock; - output [ 3:0] axi_arcache; - output [ 2:0] axi_arprot; - output [ 3:0] axi_arqos; - output [ 3:0] axi_aruser; - output [ 7:0] axi_arlen; - output [ 2:0] axi_arsize; - output [ 31:0] axi_araddr; + output [ 3:0] axi_arcache; + output [ 2:0] axi_arprot; + output [ 3:0] axi_arqos; + output [ 3:0] axi_aruser; + output [ 7:0] axi_arlen; + output [ 2:0] axi_arsize; + output [31:0] axi_araddr; input axi_arready; input axi_rvalid; - input [ 3:0] axi_rid; - input [ 3:0] axi_ruser; - input [ 1:0] axi_rresp; + input [ 3:0] axi_rid; + input [ 3:0] axi_ruser; + input [ 1:0] axi_rresp; input axi_rlast; input [(AXI_DATA_WIDTH-1):0] axi_rdata; output axi_rready; @@ -131,8 +131,8 @@ module axi_dacfifo_rd ( // internal registers reg [ 31:0] axi_rd_addr_h = 32'b0; - reg axi_rd = 1'b0; - reg axi_rd_active = 1'b0; + reg axi_rnext = 1'b0; + reg axi_ractive = 1'b0; reg axi_arvalid = 1'b0; reg [ 31:0] axi_araddr = 32'b0; reg [(AXI_DATA_WIDTH-1):0] axi_ddata = 'b0; @@ -151,18 +151,18 @@ module axi_dacfifo_rd ( always @(posedge axi_clk) begin if (axi_resetn == 1'b0) begin - axi_rd <= 1'b0; - axi_rd_active <= 1'b0; + axi_rnext <= 1'b0; + axi_ractive <= 1'b0; axi_xfer_req_m <= 2'b0; end else begin - if (axi_rd_active == 1'b1) begin - axi_rd <= 1'b0; + if (axi_ractive == 1'b1) begin + axi_rnext <= 1'b0; if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin - axi_rd_active <= 1'b0; + axi_ractive <= 1'b0; end end else if ((axi_ready_s == 1'b1)) begin - axi_rd <= axi_xfer_req; - axi_rd_active <= axi_xfer_req; + axi_rnext <= axi_xfer_req; + axi_ractive <= axi_xfer_req; end axi_xfer_req_m <= {axi_xfer_req_m[0], axi_xfer_req}; end @@ -193,7 +193,7 @@ module axi_dacfifo_rd ( axi_arvalid <= 1'b0; end end else begin - if (axi_rd == 1'b1) begin + if (axi_rnext == 1'b1) begin axi_arvalid <= 1'b1; end end diff --git a/library/axi_dacfifo/axi_dacfifo_wr.v b/library/axi_dacfifo/axi_dacfifo_wr.v index c3170b6e9..43a71c1b6 100644 --- a/library/axi_dacfifo/axi_dacfifo_wr.v +++ b/library/axi_dacfifo/axi_dacfifo_wr.v @@ -102,11 +102,11 @@ module axi_dacfifo_wr ( // for the syncronization buffer localparam MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16 - localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : - (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : - (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : - (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : - (DMA_MEM_ADDRESS_WIDTH - 4); + localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : + (DMA_MEM_ADDRESS_WIDTH - 4); // for the AXI interface @@ -195,7 +195,7 @@ module axi_dacfifo_wr ( reg axi_reset = 1'b0; reg axi_xfer_out = 1'b0; - reg [31:0] axi_last_addr = 'b0; + reg [31:0] axi_last_addr = 32'b0; reg axi_awvalid = 1'b0; reg [31:0] axi_awaddr = 32'b0; reg axi_xfer_init = 1'b0;