From e4988aa131f67e65ad1ace00110ab2c869d0be27 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 22 Aug 2017 22:26:57 +0200 Subject: [PATCH] adrv9371x: altera: Convert to ADI JESD204 Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204 framework. Signed-off-by: Lars-Peter Clausen --- projects/adrv9371x/a10gx/Makefile | 47 +++- projects/adrv9371x/a10gx/system_constr.sdc | 5 +- projects/adrv9371x/a10gx/system_project.tcl | 71 ++--- projects/adrv9371x/a10gx/system_top.v | 29 +- projects/adrv9371x/a10soc/Makefile | 48 +++- projects/adrv9371x/a10soc/system_constr.sdc | 8 +- projects/adrv9371x/a10soc/system_project.tcl | 71 ++--- projects/adrv9371x/a10soc/system_top.v | 29 +- projects/adrv9371x/common/adrv9371x_qsys.tcl | 264 +++++++------------ 9 files changed, 273 insertions(+), 299 deletions(-) diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile index 0dc06a7c4..48da34bac 100644 --- a/projects/adrv9371x/a10gx/Makefile +++ b/projects/adrv9371x/a10gx/Makefile @@ -22,9 +22,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../common/altera/dacfifo_qsys.tcl M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl -M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v -M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl -M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/adi_jesd204/adi_jesd204_hw.tcl M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v @@ -34,6 +32,9 @@ M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc M_DEPS += ../../../library/altera/common/up_rst_constr.sdc M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc +M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue.v +M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl +M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_hw.tcl M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v @@ -78,6 +79,44 @@ M_DEPS += ../../../library/common/up_dac_channel.v M_DEPS += ../../../library/common/up_dac_common.v M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_common.v +M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_sysref.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/jesd204_up_tx.v +M_DEPS += ../../../library/jesd204/jesd204_common/eof.v +M_DEPS += ../../../library/jesd204/jesd204_common/lmfc.v +M_DEPS += ../../../library/jesd204/jesd204_common/pipeline_stage.v +M_DEPS += ../../../library/jesd204/jesd204_common/scrambler.v +M_DEPS += ../../../library/jesd204/jesd204_rx/align_mux.v +M_DEPS += ../../../library/jesd204/jesd204_rx/elastic_buffer.v +M_DEPS += ../../../library/jesd204/jesd204_rx/ilas_monitor.v +M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_constr.sdc +M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_rx/lane_latency_monitor.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx_cgs.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx_ctrl.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx_lane.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_constr.sdc +M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_tx/tx.v +M_DEPS += ../../../library/jesd204/jesd204_tx/tx_ctrl.v +M_DEPS += ../../../library/jesd204/jesd204_tx/tx_lane.v M_DEPS += ../../../library/scripts/adi_env.tcl M_DEPS += ../../../library/scripts/adi_ip_alt.tcl M_DEPS += ../../../library/util_axis_fifo/address_gray.v @@ -86,6 +125,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_sync.v M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/util_cdc/sync_data.v +M_DEPS += ../../../library/util_cdc/sync_event.v M_DEPS += ../../../library/util_cdc/sync_gray.v M_DEPS += ../../../library/util_cpack/util_cpack.v M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc index 1f1249876..49f364180 100644 --- a/projects/adrv9371x/a10gx/system_constr.sdc +++ b/projects/adrv9371x/a10gx/system_constr.sdc @@ -1,13 +1,12 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "8.138 ns" -name ref_clk0 [get_ports {ref_clk0}] +create_clock -period "8.138 ns" -name ref_clk1 [get_ports {ref_clk1}] derive_pll_clocks derive_clock_uncertainty set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] -set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] -set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*] if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} { set_max_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.150 diff --git a/projects/adrv9371x/a10gx/system_project.tcl b/projects/adrv9371x/a10gx/system_project.tcl index 6ad5f9271..037dc1a91 100644 --- a/projects/adrv9371x/a10gx/system_project.tcl +++ b/projects/adrv9371x/a10gx/system_project.tcl @@ -8,52 +8,40 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl # lane interface -set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P -set_location_assignment PIN_AL7 -to "ref_clk0(n)" ; ## D05 FMCA_GBTCLK0_M2C_N -set_location_assignment PIN_AJ8 -to ref_clk1 ; ## B20 FMCA_GBTCLK1_M2C_P -set_location_assignment PIN_AJ7 -to "ref_clk1(n)" ; ## B21 FMCA_GBTCLK1_M2C_N -set_location_assignment PIN_BA7 -to rx_data[0] ; ## A02 FMCA_DP1_M2C_P -set_location_assignment PIN_BA8 -to "rx_data[0](n)" ; ## A03 FMCA_DP1_M2C_N -set_location_assignment PIN_AY5 -to rx_data[1] ; ## A06 FMCA_DP2_M2C_P -set_location_assignment PIN_AY6 -to "rx_data[1](n)" ; ## A07 FMCA_DP2_M2C_N -set_location_assignment PIN_AW7 -to rx_data[2] ; ## C06 FMCA_DP0_M2C_P -set_location_assignment PIN_AW8 -to "rx_data[2](n)" ; ## C07 FMCA_DP0_M2C_N -set_location_assignment PIN_AV5 -to rx_data[3] ; ## A10 FMCA_DP3_M2C_P -set_location_assignment PIN_AV6 -to "rx_data[3](n)" ; ## A11 FMCA_DP3_M2C_N -set_location_assignment PIN_BD5 -to tx_data[0] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[0]) -set_location_assignment PIN_BD6 -to "tx_data[0](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[0]) -set_location_assignment PIN_BB5 -to tx_data[1] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1]) -set_location_assignment PIN_BB6 -to "tx_data[1](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1]) -set_location_assignment PIN_BC7 -to tx_data[2] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[2]) -set_location_assignment PIN_BC8 -to "tx_data[2](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[2]) -set_location_assignment PIN_BC3 -to tx_data[3] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[3]) -set_location_assignment PIN_BC4 -to "tx_data[3](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[3]) +set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P +set_location_assignment PIN_AL7 -to "ref_clk0(n)" ; ## D05 FMCA_GBTCLK0_M2C_N +set_location_assignment PIN_AJ8 -to ref_clk1 ; ## B20 FMCA_GBTCLK1_M2C_P +set_location_assignment PIN_AJ7 -to "ref_clk1(n)" ; ## B21 FMCA_GBTCLK1_M2C_N +set_location_assignment PIN_BA7 -to rx_serial_data[0] ; ## A02 FMCA_DP1_M2C_P +set_location_assignment PIN_BA8 -to "rx_serial_data[0](n)" ; ## A03 FMCA_DP1_M2C_N +set_location_assignment PIN_AY5 -to rx_serial_data[1] ; ## A06 FMCA_DP2_M2C_P +set_location_assignment PIN_AY6 -to "rx_serial_data[1](n)" ; ## A07 FMCA_DP2_M2C_N +set_location_assignment PIN_AW7 -to rx_serial_data[2] ; ## C06 FMCA_DP0_M2C_P +set_location_assignment PIN_AW8 -to "rx_serial_data[2](n)" ; ## C07 FMCA_DP0_M2C_N +set_location_assignment PIN_AV5 -to rx_serial_data[3] ; ## A10 FMCA_DP3_M2C_P +set_location_assignment PIN_AV6 -to "rx_serial_data[3](n)" ; ## A11 FMCA_DP3_M2C_N +set_location_assignment PIN_BD5 -to tx_serial_data[0] ; ## A22 FMCA_DP1_C2M_P (tx_serial_data_p[0]) +set_location_assignment PIN_BD6 -to "tx_serial_data[0](n)" ; ## A23 FMCA_DP1_C2M_N (tx_serial_data_n[0]) +set_location_assignment PIN_BB5 -to tx_serial_data[1] ; ## A26 FMCA_DP2_C2M_P (tx_serial_data_p[1]) +set_location_assignment PIN_BB6 -to "tx_serial_data[1](n)" ; ## A27 FMCA_DP2_C2M_N (tx_serial_data_n[1]) +set_location_assignment PIN_BC7 -to tx_serial_data[2] ; ## C02 FMCA_DP0_C2M_P (tx_serial_data_p[2]) +set_location_assignment PIN_BC8 -to "tx_serial_data[2](n)" ; ## C03 FMCA_DP0_C2M_N (tx_serial_data_n[2]) +set_location_assignment PIN_BC3 -to tx_serial_data[3] ; ## A30 FMCA_DP3_C2M_P (tx_serial_data_p[3]) +set_location_assignment PIN_BC4 -to "tx_serial_data[3](n)" ; ## A31 FMCA_DP3_C2M_N (tx_serial_data_n[3]) -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk0 -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk1 -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] - -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] +# Merge RX and TX into single transceiver +for {set i 0} {$i < 4} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] +} set_location_assignment PIN_AR20 -to rx_sync ; ## G09 FMCA_HPC_LA03_P set_location_assignment PIN_AR19 -to rx_sync(n) ; ## G10 FMCA_HPC_LA03_N @@ -146,4 +134,3 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17] set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18] execute_flow -compile - diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v index 16073e7bc..526614ffa 100644 --- a/projects/adrv9371x/a10gx/system_top.v +++ b/projects/adrv9371x/a10gx/system_top.v @@ -81,8 +81,8 @@ module system_top ( input ref_clk0, input ref_clk1, - input [ 3:0] rx_data, - output [ 3:0] tx_data, + input [ 3:0] rx_serial_data, + output [ 3:0] tx_serial_data, output rx_sync, output rx_os_sync, input tx_sync, @@ -159,16 +159,6 @@ module system_top ( system_bd i_system_bd ( .ad9371_gpio_export (ad9371_gpio), - .rx_data_0_rx_serial_data (rx_data[0]), - .rx_data_1_rx_serial_data (rx_data[1]), - .rx_data_2_rx_serial_data (rx_data[2]), - .rx_data_3_rx_serial_data (rx_data[3]), - .rx_os_ref_clk_clk (ref_clk1), - .rx_os_sync_export (rx_os_sync), - .rx_os_sysref_export (sysref), - .rx_ref_clk_clk (ref_clk1), - .rx_sync_export (rx_sync), - .rx_sysref_export (sysref), .sys_clk_clk (sys_clk), .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), @@ -204,14 +194,19 @@ module system_top ( .sys_spi_MOSI (spi_mosi), .sys_spi_SCLK (spi_clk), .sys_spi_SS_n (spi_csn_s), - .tx_data_0_tx_serial_data (tx_data[0]), - .tx_data_1_tx_serial_data (tx_data[1]), - .tx_data_2_tx_serial_data (tx_data[2]), - .tx_data_3_tx_serial_data (tx_data[3]), + .tx_serial_data_tx_serial_data (tx_serial_data), .tx_fifo_bypass_bypass (dac_fifo_bypass), .tx_ref_clk_clk (ref_clk1), .tx_sync_export (tx_sync), - .tx_sysref_export (sysref)); + .tx_sysref_export (sysref), + .rx_serial_data_rx_serial_data (rx_serial_data[1:0]), + .rx_os_serial_data_rx_serial_data (rx_serial_data[3:2]), + .rx_os_ref_clk_clk (ref_clk1), + .rx_os_sync_export (rx_os_sync), + .rx_os_sysref_export (sysref), + .rx_ref_clk_clk (ref_clk1), + .rx_sync_export (rx_sync), + .rx_sysref_export (sysref)); endmodule diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile index 083ecb96a..0a40fac87 100644 --- a/projects/adrv9371x/a10soc/Makefile +++ b/projects/adrv9371x/a10soc/Makefile @@ -23,9 +23,7 @@ M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl -M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v -M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl -M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/adi_jesd204/adi_jesd204_hw.tcl M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo.v M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v @@ -37,12 +35,14 @@ M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v M_DEPS += ../../../library/altera/common/ad_dcfilter.v -M_DEPS += ../../../library/altera/common/ad_mem_asym.v M_DEPS += ../../../library/altera/common/ad_mul.v M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc M_DEPS += ../../../library/altera/common/up_rst_constr.sdc M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc +M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue.v +M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl +M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_hw.tcl M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v @@ -90,6 +90,44 @@ M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v M_DEPS += ../../../library/common/util_dacfifo_bypass.v M_DEPS += ../../../library/common/util_delay.v +M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_common.v +M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_sysref.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx.v +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/jesd204_up_tx.v +M_DEPS += ../../../library/jesd204/jesd204_common/eof.v +M_DEPS += ../../../library/jesd204/jesd204_common/lmfc.v +M_DEPS += ../../../library/jesd204/jesd204_common/pipeline_stage.v +M_DEPS += ../../../library/jesd204/jesd204_common/scrambler.v +M_DEPS += ../../../library/jesd204/jesd204_rx/align_mux.v +M_DEPS += ../../../library/jesd204/jesd204_rx/elastic_buffer.v +M_DEPS += ../../../library/jesd204/jesd204_rx/ilas_monitor.v +M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_constr.sdc +M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_rx/lane_latency_monitor.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx_cgs.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx_ctrl.v +M_DEPS += ../../../library/jesd204/jesd204_rx/rx_lane.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v +M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_constr.sdc +M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_hw.tcl +M_DEPS += ../../../library/jesd204/jesd204_tx/tx.v +M_DEPS += ../../../library/jesd204/jesd204_tx/tx_ctrl.v +M_DEPS += ../../../library/jesd204/jesd204_tx/tx_lane.v M_DEPS += ../../../library/scripts/adi_env.tcl M_DEPS += ../../../library/scripts/adi_ip_alt.tcl M_DEPS += ../../../library/util_axis_fifo/address_gray.v @@ -98,6 +136,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_sync.v M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/util_cdc/sync_data.v +M_DEPS += ../../../library/util_cdc/sync_event.v M_DEPS += ../../../library/util_cdc/sync_gray.v M_DEPS += ../../../library/util_cpack/util_cpack.v M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc index 808c0249a..029c5d9b2 100644 --- a/projects/adrv9371x/a10soc/system_constr.sdc +++ b/projects/adrv9371x/a10soc/system_constr.sdc @@ -1,7 +1,7 @@ -# qsys- automatically infers these clocks - create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "8.138 ns" -name ref_clk0 [get_ports {ref_clk0}] +create_clock -period "8.138 ns" -name ref_clk1 [get_ports {ref_clk1}] derive_pll_clocks derive_clock_uncertainty @@ -9,7 +9,3 @@ derive_clock_uncertainty set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] -set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] -set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*] - diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl index 15c86044b..7e16a6631 100644 --- a/projects/adrv9371x/a10soc/system_project.tcl +++ b/projects/adrv9371x/a10soc/system_project.tcl @@ -9,52 +9,40 @@ source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl # ad9371 -set_location_assignment PIN_N29 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC) -set_location_assignment PIN_N28 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC) -set_location_assignment PIN_R29 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_location_assignment PIN_R28 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_location_assignment PIN_R33 -to rx_data[0] ; ## A02 FMC_HPC_DP1_M2C_P -set_location_assignment PIN_R32 -to "rx_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N -set_location_assignment PIN_P35 -to rx_data[1] ; ## A06 FMC_HPC_DP2_M2C_P -set_location_assignment PIN_P34 -to "rx_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N -set_location_assignment PIN_T31 -to rx_data[2] ; ## C06 FMC_HPC_DP0_M2C_P -set_location_assignment PIN_T30 -to "rx_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N -set_location_assignment PIN_P31 -to rx_data[3] ; ## A10 FMC_HPC_DP3_M2C_P -set_location_assignment PIN_P30 -to "rx_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N -set_location_assignment PIN_M39 -to tx_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3]) -set_location_assignment PIN_M38 -to "tx_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3]) -set_location_assignment PIN_L37 -to tx_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0]) -set_location_assignment PIN_L36 -to "tx_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0]) -set_location_assignment PIN_N37 -to tx_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1]) -set_location_assignment PIN_N36 -to "tx_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1]) -set_location_assignment PIN_K39 -to tx_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2]) -set_location_assignment PIN_K38 -to "tx_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2]) +set_location_assignment PIN_N29 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC) +set_location_assignment PIN_N28 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC) +set_location_assignment PIN_R29 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_location_assignment PIN_R28 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_location_assignment PIN_R33 -to rx_serial_data[0] ; ## A02 FMC_HPC_DP1_M2C_P +set_location_assignment PIN_R32 -to "rx_serial_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N +set_location_assignment PIN_P35 -to rx_serial_data[1] ; ## A06 FMC_HPC_DP2_M2C_P +set_location_assignment PIN_P34 -to "rx_serial_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N +set_location_assignment PIN_T31 -to rx_serial_data[2] ; ## C06 FMC_HPC_DP0_M2C_P +set_location_assignment PIN_T30 -to "rx_serial_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N +set_location_assignment PIN_P31 -to rx_serial_data[3] ; ## A10 FMC_HPC_DP3_M2C_P +set_location_assignment PIN_P30 -to "rx_serial_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N +set_location_assignment PIN_M39 -to tx_serial_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_serial_data_p[3]) +set_location_assignment PIN_M38 -to "tx_serial_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_serial_data_n[3]) +set_location_assignment PIN_L37 -to tx_serial_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_serial_data_p[0]) +set_location_assignment PIN_L36 -to "tx_serial_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_serial_data_n[0]) +set_location_assignment PIN_N37 -to tx_serial_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_serial_data_p[1]) +set_location_assignment PIN_N36 -to "tx_serial_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_serial_data_n[1]) +set_location_assignment PIN_K39 -to tx_serial_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_serial_data_p[2]) +set_location_assignment PIN_K38 -to "tx_serial_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_serial_data_n[2]) -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk0 -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk1 -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data -set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2] -set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] - -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] -set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] +# Merge RX and TX into single transceiver +for {set i 0} {$i < 4} {incr i} { + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}] + set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}] +} set_location_assignment PIN_C14 -to rx_sync ; ## G09 FMC_HPC_LA03_P set_location_assignment PIN_D14 -to rx_sync(n) ; ## G10 FMC_HPC_LA03_N @@ -147,4 +135,3 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17] set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18] execute_flow -compile - diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v index f4ba46649..abb8d18b9 100644 --- a/projects/adrv9371x/a10soc/system_top.v +++ b/projects/adrv9371x/a10soc/system_top.v @@ -132,8 +132,8 @@ module system_top ( input ref_clk0, input ref_clk1, - input [ 3:0] rx_data, - output [ 3:0] tx_data, + input [ 3:0] rx_serial_data, + output [ 3:0] tx_serial_data, output rx_sync, output rx_os_sync, input tx_sync, @@ -212,16 +212,6 @@ module system_top ( system_bd i_system_bd ( .ad9371_gpio_export (ad9371_gpio), - .rx_data_0_rx_serial_data (rx_data[0]), - .rx_data_1_rx_serial_data (rx_data[1]), - .rx_data_2_rx_serial_data (rx_data[2]), - .rx_data_3_rx_serial_data (rx_data[3]), - .rx_os_ref_clk_clk (ref_clk1), - .rx_os_sync_export (rx_os_sync), - .rx_os_sysref_export (sysref), - .rx_ref_clk_clk (ref_clk1), - .rx_sync_export (rx_sync), - .rx_sysref_export (sysref), .sys_clk_clk (sys_clk), .sys_ddr_mem_mem_ck (sys_ddr_clk_p), .sys_ddr_mem_mem_ck_n (sys_ddr_clk_n), @@ -317,14 +307,19 @@ module system_top ( .sys_spi_MOSI (spi_mosi), .sys_spi_SCLK (spi_clk), .sys_spi_SS_n (spi_csn_s), - .tx_data_0_tx_serial_data (tx_data[0]), - .tx_data_1_tx_serial_data (tx_data[1]), - .tx_data_2_tx_serial_data (tx_data[2]), - .tx_data_3_tx_serial_data (tx_data[3]), + .tx_serial_data_tx_serial_data (tx_serial_data), .tx_fifo_bypass_bypass (dac_fifo_bypass), .tx_ref_clk_clk (ref_clk1), .tx_sync_export (tx_sync), - .tx_sysref_export (sysref)); + .tx_sysref_export (sysref), + .rx_serial_data_rx_serial_data (rx_serial_data[1:0]), + .rx_os_serial_data_rx_serial_data (rx_serial_data[3:2]), + .rx_os_ref_clk_clk (ref_clk1), + .rx_os_sync_export (rx_os_sync), + .rx_os_sysref_export (sysref), + .rx_ref_clk_clk (ref_clk1), + .rx_sync_export (rx_sync), + .rx_sysref_export (sysref)); endmodule diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl index e085ba247..bc8f473d5 100644 --- a/projects/adrv9371x/common/adrv9371x_qsys.tcl +++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl @@ -1,138 +1,79 @@ -# ad9371_tx-xcvr +# ad9371_tx JESD204 -add_instance avl_ad9371_tx_xcvr avl_adxcvr -set_instance_parameter_value avl_ad9371_tx_xcvr {ID} {0} -set_instance_parameter_value avl_ad9371_tx_xcvr {TX_OR_RX_N} {1} -set_instance_parameter_value avl_ad9371_tx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} -set_instance_parameter_value avl_ad9371_tx_xcvr {LANE_RATE} {4915.2} -set_instance_parameter_value avl_ad9371_tx_xcvr {REFCLK_FREQUENCY} {122.88} -set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_LANES} {4} -set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_CONVS} {4} -set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_BCNT} {2} -set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_SCNT} {1} -set_instance_parameter_value avl_ad9371_tx_xcvr {MF_FCNT} {32} -set_instance_parameter_value avl_ad9371_tx_xcvr {HD} {1} -set_instance_parameter_value avl_ad9144_xcvr {TX_LANE_MAP} {3 0 1 2} +add_instance ad9371_tx_jesd204 adi_jesd204 +set_instance_parameter_value ad9371_tx_jesd204 {ID} {0} +set_instance_parameter_value ad9371_tx_jesd204 {TX_OR_RX_N} {1} +set_instance_parameter_value ad9371_tx_jesd204 {LANE_RATE} {4915.2} +set_instance_parameter_value ad9371_tx_jesd204 {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value ad9371_tx_jesd204 {NUM_OF_LANES} {4} +set_instance_parameter_value ad9371_tx_jesd204 {LANE_MAP} {3 0 1 2} +set_instance_parameter_value ad9371_tx_jesd204 {SOFT_PCS} {false} -add_connection sys_clk.clk avl_ad9371_tx_xcvr.sys_clk -add_connection sys_clk.clk_reset avl_ad9371_tx_xcvr.sys_resetn +add_connection sys_clk.clk ad9371_tx_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9371_tx_jesd204.sys_resetn add_interface tx_ref_clk clock sink -set_interface_property tx_ref_clk EXPORT_OF avl_ad9371_tx_xcvr.ref_clk -add_interface tx_data_0 conduit end -set_interface_property tx_data_0 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_0 -add_interface tx_data_1 conduit end -set_interface_property tx_data_1 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_1 -add_interface tx_data_2 conduit end -set_interface_property tx_data_2 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_2 -add_interface tx_data_3 conduit end -set_interface_property tx_data_3 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_3 +set_interface_property tx_ref_clk EXPORT_OF ad9371_tx_jesd204.ref_clk +add_interface tx_serial_data conduit end +set_interface_property tx_serial_data EXPORT_OF ad9371_tx_jesd204.serial_data add_interface tx_sysref conduit end -set_interface_property tx_sysref EXPORT_OF avl_ad9371_tx_xcvr.sysref +set_interface_property tx_sysref EXPORT_OF ad9371_tx_jesd204.sysref add_interface tx_sync conduit end -set_interface_property tx_sync EXPORT_OF avl_ad9371_tx_xcvr.sync +set_interface_property tx_sync EXPORT_OF ad9371_tx_jesd204.sync -# ad9371_tx-xcvr +# ad9371_rx JESD204 -add_instance axi_ad9371_tx_xcvr axi_adxcvr -set_instance_parameter_value axi_ad9371_tx_xcvr {ID} {0} -set_instance_parameter_value axi_ad9371_tx_xcvr {TX_OR_RX_N} {1} -set_instance_parameter_value axi_ad9371_tx_xcvr {NUM_OF_LANES} {4} -add_connection sys_clk.clk axi_ad9371_tx_xcvr.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9371_tx_xcvr.s_axi_reset -add_connection axi_ad9371_tx_xcvr.if_up_rst avl_ad9371_tx_xcvr.rst -add_connection avl_ad9371_tx_xcvr.ready axi_ad9371_tx_xcvr.ready -add_connection axi_ad9371_tx_xcvr.core_pll_locked avl_ad9371_tx_xcvr.core_pll_locked +add_instance ad9371_rx_jesd204 adi_jesd204 +set_instance_parameter_value ad9371_rx_jesd204 {ID} {1} +set_instance_parameter_value ad9371_rx_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9371_rx_jesd204 {LANE_RATE} {4915.2} +set_instance_parameter_value ad9371_rx_jesd204 {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value ad9371_rx_jesd204 {NUM_OF_LANES} {2} +set_instance_parameter_value ad9371_rx_jesd204 {SOFT_PCS} {false} -# ad9371_rx-xcvr - -add_instance avl_ad9371_rx_xcvr avl_adxcvr -set_instance_parameter_value avl_ad9371_rx_xcvr {ID} {1} -set_instance_parameter_value avl_ad9371_rx_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value avl_ad9371_rx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} -set_instance_parameter_value avl_ad9371_rx_xcvr {LANE_RATE} {4915.2} -set_instance_parameter_value avl_ad9371_rx_xcvr {REFCLK_FREQUENCY} {122.88} -set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_LANES} {2} -set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_CONVS} {4} -set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_BCNT} {4} -set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_SCNT} {1} -set_instance_parameter_value avl_ad9371_rx_xcvr {MF_FCNT} {32} -set_instance_parameter_value avl_ad9371_rx_xcvr {HD} {1} -add_connection sys_clk.clk avl_ad9371_rx_xcvr.sys_clk -add_connection sys_clk.clk_reset avl_ad9371_rx_xcvr.sys_resetn +add_connection sys_clk.clk ad9371_rx_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9371_rx_jesd204.sys_resetn add_interface rx_ref_clk clock sink -set_interface_property rx_ref_clk EXPORT_OF avl_ad9371_rx_xcvr.ref_clk -add_interface rx_data_0 conduit end -set_interface_property rx_data_0 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_0 -add_interface rx_data_1 conduit end -set_interface_property rx_data_1 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_1 +set_interface_property rx_ref_clk EXPORT_OF ad9371_rx_jesd204.ref_clk +add_interface rx_serial_data conduit end +set_interface_property rx_serial_data EXPORT_OF ad9371_rx_jesd204.serial_data add_interface rx_sysref conduit end -set_interface_property rx_sysref EXPORT_OF avl_ad9371_rx_xcvr.sysref +set_interface_property rx_sysref EXPORT_OF ad9371_rx_jesd204.sysref add_interface rx_sync conduit end -set_interface_property rx_sync EXPORT_OF avl_ad9371_rx_xcvr.sync +set_interface_property rx_sync EXPORT_OF ad9371_rx_jesd204.sync -# ad9371_rx-xcvr +# ad9371_rx_os JESD204 -add_instance axi_ad9371_rx_xcvr axi_adxcvr -set_instance_parameter_value axi_ad9371_rx_xcvr {ID} {1} -set_instance_parameter_value axi_ad9371_rx_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value axi_ad9371_rx_xcvr {NUM_OF_LANES} {2} -add_connection sys_clk.clk axi_ad9371_rx_xcvr.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9371_rx_xcvr.s_axi_reset -add_connection axi_ad9371_rx_xcvr.if_up_rst avl_ad9371_rx_xcvr.rst -add_connection avl_ad9371_rx_xcvr.ready axi_ad9371_rx_xcvr.ready -add_connection axi_ad9371_rx_xcvr.core_pll_locked avl_ad9371_rx_xcvr.core_pll_locked +add_instance ad9371_rx_os_jesd204 adi_jesd204 +set_instance_parameter_value ad9371_rx_os_jesd204 {ID} {1} +set_instance_parameter_value ad9371_rx_os_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9371_rx_os_jesd204 {LANE_RATE} {4915.2} +set_instance_parameter_value ad9371_rx_os_jesd204 {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value ad9371_rx_os_jesd204 {SOFT_PCS} {false} +set_instance_parameter_value ad9371_rx_os_jesd204 {NUM_OF_LANES} {2} -# ad9371_rx_os-xcvr - -add_instance avl_ad9371_rx_os_xcvr avl_adxcvr -set_instance_parameter_value avl_ad9371_rx_os_xcvr {ID} {1} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {LANE_RATE} {4915.2} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {REFCLK_FREQUENCY} {122.88} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_LANES} {2} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_CONVS} {2} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_BCNT} {2} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_SCNT} {1} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {MF_FCNT} {32} -set_instance_parameter_value avl_ad9371_rx_os_xcvr {HD} {1} -add_connection sys_clk.clk avl_ad9371_rx_os_xcvr.sys_clk -add_connection sys_clk.clk_reset avl_ad9371_rx_os_xcvr.sys_resetn +add_connection sys_clk.clk ad9371_rx_os_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9371_rx_os_jesd204.sys_resetn add_interface rx_os_ref_clk clock sink -set_interface_property rx_os_ref_clk EXPORT_OF avl_ad9371_rx_os_xcvr.ref_clk -add_interface rx_data_2 conduit end -set_interface_property rx_data_2 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_0 -add_interface rx_data_3 conduit end -set_interface_property rx_data_3 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_1 +set_interface_property rx_os_ref_clk EXPORT_OF ad9371_rx_os_jesd204.ref_clk +add_interface rx_os_serial_data conduit end +set_interface_property rx_os_serial_data EXPORT_OF ad9371_rx_os_jesd204.serial_data add_interface rx_os_sysref conduit end -set_interface_property rx_os_sysref EXPORT_OF avl_ad9371_rx_os_xcvr.sysref +set_interface_property rx_os_sysref EXPORT_OF ad9371_rx_os_jesd204.sysref add_interface rx_os_sync conduit end -set_interface_property rx_os_sync EXPORT_OF avl_ad9371_rx_os_xcvr.sync - -# ad9371_rx_os-xcvr - -add_instance axi_ad9371_rx_os_xcvr axi_adxcvr -set_instance_parameter_value axi_ad9371_rx_os_xcvr {ID} {2} -set_instance_parameter_value axi_ad9371_rx_os_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value axi_ad9371_rx_os_xcvr {NUM_OF_LANES} {2} -add_connection sys_clk.clk axi_ad9371_rx_os_xcvr.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9371_rx_os_xcvr.s_axi_reset -add_connection axi_ad9371_rx_os_xcvr.if_up_rst avl_ad9371_rx_os_xcvr.rst -add_connection avl_ad9371_rx_os_xcvr.ready axi_ad9371_rx_os_xcvr.ready -add_connection axi_ad9371_rx_os_xcvr.core_pll_locked avl_ad9371_rx_os_xcvr.core_pll_locked +set_interface_property rx_os_sync EXPORT_OF ad9371_rx_os_jesd204.sync # ad9371-core add_instance axi_ad9371 axi_ad9371 -add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371.if_dac_clk -add_connection axi_ad9371.if_dac_tx_data avl_ad9371_tx_xcvr.ip_data -add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371.if_adc_clk -add_connection avl_ad9371_rx_xcvr.ip_sof axi_ad9371.if_adc_rx_sof -add_connection avl_ad9371_rx_xcvr.ip_data axi_ad9371.if_adc_rx_data -add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371.if_adc_os_clk -add_connection avl_ad9371_rx_os_xcvr.ip_sof axi_ad9371.if_adc_rx_os_sof -add_connection avl_ad9371_rx_os_xcvr.ip_data axi_ad9371.if_adc_rx_os_data +add_connection ad9371_tx_jesd204.link_clk axi_ad9371.if_dac_clk +add_connection axi_ad9371.if_dac_tx_data ad9371_tx_jesd204.link_data +add_connection ad9371_rx_jesd204.link_clk axi_ad9371.if_adc_clk +add_connection ad9371_rx_jesd204.link_sof axi_ad9371.if_adc_rx_sof +add_connection ad9371_rx_jesd204.link_data axi_ad9371.if_adc_rx_data +add_connection ad9371_rx_os_jesd204.link_clk axi_ad9371.if_adc_os_clk +add_connection ad9371_rx_os_jesd204.link_sof axi_ad9371.if_adc_rx_os_sof +add_connection ad9371_rx_os_jesd204.link_data axi_ad9371.if_adc_rx_os_data add_connection sys_clk.clk axi_ad9371.s_axi_clock add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset @@ -141,7 +82,7 @@ add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset add_instance axi_ad9371_tx_upack util_upack set_instance_parameter_value axi_ad9371_tx_upack {NUM_OF_CHANNELS} {4} set_instance_parameter_value axi_ad9371_tx_upack {CHANNEL_DATA_WIDTH} {32} -add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_upack.if_dac_clk +add_connection ad9371_tx_jesd204.link_clk axi_ad9371_tx_upack.if_dac_clk add_connection axi_ad9371_tx_upack.dac_ch_0 axi_ad9371.dac_ch_0 add_connection axi_ad9371_tx_upack.dac_ch_1 axi_ad9371.dac_ch_1 add_connection axi_ad9371_tx_upack.dac_ch_2 axi_ad9371.dac_ch_2 @@ -151,7 +92,7 @@ add_instance axi_ad9371_rx_cpack util_cpack set_instance_parameter_value axi_ad9371_rx_cpack {NUM_OF_CHANNELS} {4} set_instance_parameter_value axi_ad9371_rx_cpack {CHANNEL_DATA_WIDTH} {16} add_connection sys_clk.clk_reset axi_ad9371_rx_cpack.if_adc_rst -add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_cpack.if_adc_clk +add_connection ad9371_rx_jesd204.link_clk axi_ad9371_rx_cpack.if_adc_clk add_connection axi_ad9371.adc_ch_0 axi_ad9371_rx_cpack.adc_ch_0 add_connection axi_ad9371.adc_ch_1 axi_ad9371_rx_cpack.adc_ch_1 add_connection axi_ad9371.adc_ch_2 axi_ad9371_rx_cpack.adc_ch_2 @@ -161,7 +102,7 @@ add_instance axi_ad9371_rx_os_cpack util_cpack set_instance_parameter_value axi_ad9371_rx_os_cpack {NUM_OF_CHANNELS} {2} set_instance_parameter_value axi_ad9371_rx_os_cpack {CHANNEL_DATA_WIDTH} {32} add_connection sys_clk.clk_reset axi_ad9371_rx_os_cpack.if_adc_rst -add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_cpack.if_adc_clk +add_connection ad9371_rx_os_jesd204.link_clk axi_ad9371_rx_os_cpack.if_adc_clk add_connection axi_ad9371.adc_os_ch_0 axi_ad9371_rx_os_cpack.adc_ch_0 add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1 @@ -170,8 +111,8 @@ add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1 add_interface tx_fifo_bypass conduit end set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9371_tx_fifo.if_bypass -add_connection axi_ad9371_tx_xcvr.if_up_rst avl_ad9371_tx_fifo.if_dac_rst -add_connection avl_ad9371_tx_xcvr.core_clk avl_ad9371_tx_fifo.if_dac_clk +add_connection ad9371_tx_jesd204.link_clk avl_ad9371_tx_fifo.if_dac_clk +add_connection ad9371_tx_jesd204.link_reset avl_ad9371_tx_fifo.if_dac_rst add_connection axi_ad9371_tx_upack.if_dac_valid avl_ad9371_tx_fifo.if_dac_valid add_connection avl_ad9371_tx_fifo.if_dac_data axi_ad9371_tx_upack.if_dac_data add_connection avl_ad9371_tx_fifo.if_dac_dunf axi_ad9371.if_dac_dunf @@ -217,7 +158,7 @@ set_instance_parameter_value axi_ad9371_rx_dma {CYCLIC} {0} set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_DEST} {0} set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {2} set_instance_parameter_value axi_ad9371_rx_dma {FIFO_SIZE} {16} -add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_dma.if_fifo_wr_clk +add_connection ad9371_rx_jesd204.link_clk axi_ad9371_rx_dma.if_fifo_wr_clk add_connection axi_ad9371_rx_cpack.if_adc_valid axi_ad9371_rx_dma.if_fifo_wr_en add_connection axi_ad9371_rx_cpack.if_adc_sync axi_ad9371_rx_dma.if_fifo_wr_sync add_connection axi_ad9371_rx_cpack.if_adc_data axi_ad9371_rx_dma.if_fifo_wr_din @@ -240,7 +181,7 @@ set_instance_parameter_value axi_ad9371_rx_os_dma {CYCLIC} {0} set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_DEST} {0} set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {2} set_instance_parameter_value axi_ad9371_rx_os_dma {FIFO_SIZE} {16} -add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_dma.if_fifo_wr_clk +add_connection ad9371_rx_os_jesd204.link_clk axi_ad9371_rx_os_dma.if_fifo_wr_clk add_connection axi_ad9371_rx_os_cpack.if_adc_valid axi_ad9371_rx_os_dma.if_fifo_wr_en add_connection axi_ad9371_rx_os_cpack.if_adc_sync axi_ad9371_rx_os_dma.if_fifo_wr_sync add_connection axi_ad9371_rx_os_cpack.if_adc_data axi_ad9371_rx_os_dma.if_fifo_wr_din @@ -263,55 +204,48 @@ set_interface_property ad9371_gpio EXPORT_OF avl_ad9371_gpio.external_connection # reconfig sharing -add_instance avl_adxcfg_0 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n -add_connection avl_adxcfg_0.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_0 -add_connection avl_adxcfg_0.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_0 +for {set i 0} {$i < 4} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 ad9371_tx_jesd204.phy_reconfig_${i} -add_instance avl_adxcfg_1 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n -add_connection avl_adxcfg_1.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_1 -add_connection avl_adxcfg_1.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_1 - -add_instance avl_adxcfg_2 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n -add_connection avl_adxcfg_2.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_2 -add_connection avl_adxcfg_2.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_0 - -add_instance avl_adxcfg_3 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n -add_connection avl_adxcfg_3.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_3 -add_connection avl_adxcfg_3.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_1 + if {$i < 2} { + add_connection avl_adxcfg_${i}.rcfg_m1 ad9371_rx_jesd204.phy_reconfig_${i} + } else { + set j [expr $i - 2] + add_connection avl_adxcfg_${i}.rcfg_m1 ad9371_rx_os_jesd204.phy_reconfig_${j} + } +} # addresses -ad_cpu_interconnect 0x00010000 avl_adxcfg_0.rcfg_s0 -ad_cpu_interconnect 0x00011000 avl_adxcfg_0.rcfg_s1 -ad_cpu_interconnect 0x00012000 avl_adxcfg_1.rcfg_s0 -ad_cpu_interconnect 0x00013000 avl_adxcfg_1.rcfg_s1 -ad_cpu_interconnect 0x00014000 avl_adxcfg_2.rcfg_s0 -ad_cpu_interconnect 0x00015000 avl_adxcfg_2.rcfg_s1 -ad_cpu_interconnect 0x00016000 avl_adxcfg_3.rcfg_s0 -ad_cpu_interconnect 0x00017000 avl_adxcfg_3.rcfg_s1 -ad_cpu_interconnect 0x00018000 avl_ad9371_tx_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x00019000 avl_ad9371_tx_xcvr.ip_reconfig -ad_cpu_interconnect 0x0001a000 avl_ad9371_tx_xcvr.lane_pll_reconfig -ad_cpu_interconnect 0x0001b000 avl_ad9371_rx_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x0001c000 avl_ad9371_rx_xcvr.ip_reconfig -ad_cpu_interconnect 0x0001d000 avl_ad9371_rx_os_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x0001e000 avl_ad9371_rx_os_xcvr.ip_reconfig -ad_cpu_interconnect 0x00020000 axi_ad9371_tx_xcvr.s_axi -ad_cpu_interconnect 0x00030000 axi_ad9371_rx_xcvr.s_axi -ad_cpu_interconnect 0x00040000 axi_ad9371_rx_os_xcvr.s_axi -ad_cpu_interconnect 0x00050000 axi_ad9371_tx_dma.s_axi -ad_cpu_interconnect 0x00060000 axi_ad9371_rx_dma.s_axi -ad_cpu_interconnect 0x00070000 axi_ad9371_rx_os_dma.s_axi -ad_cpu_interconnect 0x00080000 axi_ad9371.s_axi -ad_cpu_interconnect 0x00090000 avl_ad9371_gpio.s1 +ad_cpu_interconnect 0x00020000 ad9371_tx_jesd204.link_reconfig +ad_cpu_interconnect 0x00024000 ad9371_tx_jesd204.link_management +ad_cpu_interconnect 0x00025000 ad9371_tx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00026000 ad9371_tx_jesd204.lane_pll_reconfig +ad_cpu_interconnect 0x00028000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x0002c000 axi_ad9371_tx_dma.s_axi + +ad_cpu_interconnect 0x00030000 ad9371_rx_jesd204.link_reconfig +ad_cpu_interconnect 0x00034000 ad9371_rx_jesd204.link_management +ad_cpu_interconnect 0x00035000 ad9371_rx_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x0003c000 axi_ad9371_rx_dma.s_axi + +ad_cpu_interconnect 0x00040000 ad9371_rx_os_jesd204.link_reconfig +ad_cpu_interconnect 0x00044000 ad9371_rx_os_jesd204.link_management +ad_cpu_interconnect 0x00045000 ad9371_rx_os_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00048000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x00049000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x0004c000 axi_ad9371_rx_os_dma.s_axi + +ad_cpu_interconnect 0x00050000 axi_ad9371.s_axi +ad_cpu_interconnect 0x00060000 avl_ad9371_gpio.s1 # dma interconnects