diff --git a/library/common/ad_gt_channel.v b/library/common/ad_gt_channel.v new file mode 100644 index 000000000..0eba34c62 --- /dev/null +++ b/library/common/ad_gt_channel.v @@ -0,0 +1,1478 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module ad_gt_channel ( + + // rst and clocks + + lpm_dfe_n, + cpll_ref_clk_in, + cpll_pd, + cpll_rst, + qpll_clk, + qpll_ref_clk, + qpll_locked, + + // receive + + rx_rst, + rx_p, + rx_n, + + rx_sys_clk_sel, + rx_out_clk_sel, + rx_out_clk, + rx_rst_done, + rx_rst_done_in, + rx_rst_done_out, + rx_pll_locked, + rx_pll_locked_in, + rx_pll_locked_out, + rx_user_ready, + + rx_clk, + rx_gt_charisk, + rx_gt_disperr, + rx_gt_notintable, + rx_gt_data, + rx_gt_comma_align_enb, + rx_gt_ilas_f, + rx_gt_ilas_q, + rx_gt_ilas_a, + rx_gt_ilas_r, + rx_gt_cgs_k, + + // transmit + + tx_rst, + tx_p, + tx_n, + + tx_sys_clk_sel, + tx_out_clk_sel, + tx_out_clk, + tx_rst_done, + tx_rst_done_in, + tx_rst_done_out, + tx_pll_locked, + tx_pll_locked_in, + tx_pll_locked_out, + tx_user_ready, + + tx_clk, + tx_gt_charisk, + tx_gt_data, + + // drp interface + + up_clk, + up_drp_sel, + up_drp_addr, + up_drp_wr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready, + up_drp_rxrate); + + // parameters + + parameter integer GTH_GTX_N = 0; + parameter [31:0] PMA_RSV = 32'h00018480; + parameter integer CPLL_FBDIV = 2; + parameter integer RX_OUT_DIV = 1; + parameter integer RX_CLK25_DIV = 10; + parameter integer RX_CLKBUF_ENABLE = 0; + parameter integer RX_PRIMARY = 0; + parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020; + parameter integer TX_OUT_DIV = 1; + parameter integer TX_CLK25_DIV = 10; + parameter integer TX_CLKBUF_ENABLE = 0; + parameter integer TX_PRIMARY = 0; + + // rst and clocks + + input lpm_dfe_n; + input cpll_ref_clk_in; + input cpll_pd; + input cpll_rst; + input qpll_clk; + input qpll_ref_clk; + input qpll_locked; + + // receive + + input rx_rst; + input rx_p; + input rx_n; + + input [ 1:0] rx_sys_clk_sel; + input [ 2:0] rx_out_clk_sel; + output rx_out_clk; + output rx_rst_done; + input rx_rst_done_in; + output rx_rst_done_out; + output rx_pll_locked; + input rx_pll_locked_in; + output rx_pll_locked_out; + input rx_user_ready; + + input rx_clk; + output [ 3:0] rx_gt_charisk; + output [ 3:0] rx_gt_disperr; + output [ 3:0] rx_gt_notintable; + output [31:0] rx_gt_data; + input rx_gt_comma_align_enb; + output [ 3:0] rx_gt_ilas_f; + output [ 3:0] rx_gt_ilas_q; + output [ 3:0] rx_gt_ilas_a; + output [ 3:0] rx_gt_ilas_r; + output [ 3:0] rx_gt_cgs_k; + + // transmit + + input tx_rst; + output tx_p; + output tx_n; + + input [ 1:0] tx_sys_clk_sel; + input [ 2:0] tx_out_clk_sel; + output tx_out_clk; + output tx_rst_done; + input tx_rst_done_in; + output tx_rst_done_out; + output tx_pll_locked; + input tx_pll_locked_in; + output tx_pll_locked_out; + input tx_user_ready; + + input tx_clk; + input [ 3:0] tx_gt_charisk; + input [31:0] tx_gt_data; + + // drp interface + + input up_clk; + input up_drp_sel; + input [11:0] up_drp_addr; + input up_drp_wr; + input [15:0] up_drp_wdata; + output [15:0] up_drp_rdata; + output up_drp_ready; + output [ 7:0] up_drp_rxrate; + + // internal signals + + wire [ 3:0] rx_valid_k_s; + wire [ 2:0] rx_rate_p_s; + wire [ 3:0] rx_charisk_open_s; + wire [ 3:0] rx_disperr_open_s; + wire [ 3:0] rx_notintable_open_s; + wire [31:0] rx_data_open_s; + wire [ 1:0] rx_sys_clk_sel_s; + wire [ 1:0] tx_sys_clk_sel_s; + wire [ 1:0] rx_pll_clk_sel_s; + wire [ 1:0] tx_pll_clk_sel_s; + wire rx_out_clk_s; + wire tx_out_clk_s; + wire cpll_locked_s; + + // cgs & ilas frame characters + + assign rx_gt_ilas_f[3] = (rx_gt_data[31:24] == 8'hfc) ? rx_valid_k_s[3] : 1'b0; + assign rx_gt_ilas_f[2] = (rx_gt_data[23:16] == 8'hfc) ? rx_valid_k_s[2] : 1'b0; + assign rx_gt_ilas_f[1] = (rx_gt_data[15: 8] == 8'hfc) ? rx_valid_k_s[1] : 1'b0; + assign rx_gt_ilas_f[0] = (rx_gt_data[ 7: 0] == 8'hfc) ? rx_valid_k_s[0] : 1'b0; + assign rx_gt_ilas_q[3] = (rx_gt_data[31:24] == 8'h9c) ? rx_valid_k_s[3] : 1'b0; + assign rx_gt_ilas_q[2] = (rx_gt_data[23:16] == 8'h9c) ? rx_valid_k_s[2] : 1'b0; + assign rx_gt_ilas_q[1] = (rx_gt_data[15: 8] == 8'h9c) ? rx_valid_k_s[1] : 1'b0; + assign rx_gt_ilas_q[0] = (rx_gt_data[ 7: 0] == 8'h9c) ? rx_valid_k_s[0] : 1'b0; + assign rx_gt_ilas_a[3] = (rx_gt_data[31:24] == 8'h7c) ? rx_valid_k_s[3] : 1'b0; + assign rx_gt_ilas_a[2] = (rx_gt_data[23:16] == 8'h7c) ? rx_valid_k_s[2] : 1'b0; + assign rx_gt_ilas_a[1] = (rx_gt_data[15: 8] == 8'h7c) ? rx_valid_k_s[1] : 1'b0; + assign rx_gt_ilas_a[0] = (rx_gt_data[ 7: 0] == 8'h7c) ? rx_valid_k_s[0] : 1'b0; + assign rx_gt_ilas_r[3] = (rx_gt_data[31:24] == 8'h1c) ? rx_valid_k_s[3] : 1'b0; + assign rx_gt_ilas_r[2] = (rx_gt_data[23:16] == 8'h1c) ? rx_valid_k_s[2] : 1'b0; + assign rx_gt_ilas_r[1] = (rx_gt_data[15: 8] == 8'h1c) ? rx_valid_k_s[1] : 1'b0; + assign rx_gt_ilas_r[0] = (rx_gt_data[ 7: 0] == 8'h1c) ? rx_valid_k_s[0] : 1'b0; + assign rx_gt_cgs_k[3] = (rx_gt_data[31:24] == 8'hbc) ? rx_valid_k_s[3] : 1'b0; + assign rx_gt_cgs_k[2] = (rx_gt_data[23:16] == 8'hbc) ? rx_valid_k_s[2] : 1'b0; + assign rx_gt_cgs_k[1] = (rx_gt_data[15: 8] == 8'hbc) ? rx_valid_k_s[1] : 1'b0; + assign rx_gt_cgs_k[0] = (rx_gt_data[ 7: 0] == 8'hbc) ? rx_valid_k_s[0] : 1'b0; + + // validate all characters + + assign rx_valid_k_s = rx_gt_charisk & (~rx_gt_disperr) & (~rx_gt_notintable); + + // rate + + assign rx_rate_p_s = 0; + assign up_drp_rxrate = (rx_rate_p_s == 3'd0) ? RX_OUT_DIV : + (rx_rate_p_s == 3'd1) ? 8'h01 : + (rx_rate_p_s == 3'd2) ? 8'h02 : + (rx_rate_p_s == 3'd3) ? 8'h04 : + (rx_rate_p_s == 3'd4) ? 8'h08 : + (rx_rate_p_s == 3'd5) ? 8'h10 : 8'h00; + + // pll locked + + assign rx_pll_locked = (rx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s; + assign rx_pll_locked_out = (RX_PRIMARY == 1) ? rx_pll_locked : + (rx_pll_locked & rx_pll_locked_in); + + assign tx_pll_locked = (tx_sys_clk_sel == 2'd3) ? qpll_locked : cpll_locked_s; + assign tx_pll_locked_out = (TX_PRIMARY == 1) ? tx_pll_locked : + (tx_pll_locked & tx_pll_locked_in); + + // reset done + + assign rx_rst_done_out = (RX_PRIMARY == 1) ? rx_rst_done : + (rx_rst_done & rx_rst_done_in); + + assign tx_rst_done_out = (TX_PRIMARY == 1) ? tx_rst_done : + (tx_rst_done & tx_rst_done_in); + + // instantiations + + generate + + if (RX_CLKBUF_ENABLE == 0) begin + assign rx_out_clk = rx_out_clk_s; + end + + if (TX_CLKBUF_ENABLE == 0) begin + assign tx_out_clk = tx_out_clk_s; + end + + if (GTH_GTX_N == 0) begin + + assign rx_sys_clk_sel_s = rx_sys_clk_sel; + assign tx_sys_clk_sel_s = tx_sys_clk_sel; + assign rx_pll_clk_sel_s = 2'd0; + assign tx_pll_clk_sel_s = 2'd0; + + if (RX_CLKBUF_ENABLE == 1) begin + BUFG i_bufg_rx_clk ( + .I (rx_out_clk_s), + .O (rx_out_clk)); + end + + if (TX_CLKBUF_ENABLE == 1) begin + BUFG i_bufg_tx_clk ( + .I (tx_out_clk_s), + .O (tx_out_clk)); + end + + GTXE2_CHANNEL #( + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_CPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("3.0"), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .SHOW_REALIGN_COMMA ("TRUE"), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RX_SIG_VALID_DLY (10), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (35), + .CLK_COR_MIN_LAT (31), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_LEN (1), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_1_1 (10'b0000000000), + .CLK_COR_SEQ_1_2 (10'b0000000000), + .CLK_COR_SEQ_1_3 (10'b0000000000), + .CLK_COR_SEQ_1_4 (10'b0000000000), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0000000000), + .CLK_COR_SEQ_2_2 (10'b0000000000), + .CLK_COR_SEQ_2_3 (10'b0000000000), + .CLK_COR_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (7), + .CHAN_BOND_SEQ_LEN (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER (80'h00000000000000000000), + .ES_QUAL_MASK (80'h00000000000000000000), + .ES_SDATA_MASK (80'h00000000000000000000), + .ES_VERT_OFFSET (9'b000000000), + .RX_DATA_WIDTH (40), + .OUTREFCLK_SEL_INV (2'b11), + .PMA_RSV (PMA_RSV), + .PMA_RSV2 (16'h2070), + .PMA_RSV3 (2'b00), + .PMA_RSV4 (32'h00000000), + .RX_BIAS_CFG (12'b000000000100), + .DMONITOR_CFG (24'h000A00), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (3'b010), + .RX_DEBUG_CFG (12'b000000000000), + .RX_OS_CFG (13'b0000010000000), + .TERM_RCAL_CFG (5'b10000), + .TERM_RCAL_OVRD (1'b0), + .TST_RSV (32'h00000000), + .RX_CLK25_DIV (RX_CLK25_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .UCODEER_CLR (1'b0), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD_ATTR (48'h000000000000), + .RXBUF_ADDR_MODE ("FULL"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RX_BUFFER_CFG (6'b000000), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUFRESET_TIME (5'b00001), + .RXBUF_THRESH_OVFLW (61), + .RXBUF_THRESH_OVRD ("FALSE"), + .RXBUF_THRESH_UNDFLW (4), + .RXDLY_CFG (16'h001F), + .RXDLY_LCFG (9'h030), + .RXDLY_TAP_CFG (16'h0000), + .RXPH_CFG (24'h000000), + .RXPHDLY_CFG (24'h084020), + .RXPH_MONITOR_SEL (5'b00000), + .RX_XCLK_SEL ("RXREC"), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RXCDR_CFG (RX_CDR_CFG), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCDR_LOCK_CFG (6'b010101), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXISCANRESET_TIME (5'b00001), + .RXPCSRESET_TIME (5'b00001), + .RXPMARESET_TIME (5'b00011), + .RXOOB_CFG (7'b0000110), + .RXGEARBOX_EN ("FALSE"), + .GEARBOX_MODE (3'b000), + .RXPRBS_ERR_LOOPBACK (1'b0), + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h3c), + .PD_TRANS_TIME_TO_P2 (8'h64), + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + .TRANS_TIME_RATE (8'h0E), + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h001F), + .TXDLY_LCFG (9'h030), + .TXDLY_TAP_CFG (16'h0000), + .TXPH_CFG (16'h0780), + .TXPHDLY_CFG (24'h084020), + .TXPH_MONITOR_SEL (5'b00000), + .TX_XCLK_SEL ("TXOUT"), + .TX_DATA_WIDTH (40), + .TX_DEEMPH0 (5'b00000), + .TX_DEEMPH1 (5'b00000), + .TX_EIDLE_ASSERT_DELAY (3'b110), + .TX_EIDLE_DEASSERT_DELAY (3'b100), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_DRIVE_MODE ("DIRECT"), + .TX_MARGIN_FULL_0 (7'b1001110), + .TX_MARGIN_FULL_1 (7'b1001001), + .TX_MARGIN_FULL_2 (7'b1000101), + .TX_MARGIN_FULL_3 (7'b1000010), + .TX_MARGIN_FULL_4 (7'b1000000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000100), + .TX_MARGIN_LOW_2 (7'b1000010), + .TX_MARGIN_LOW_3 (7'b1000000), + .TX_MARGIN_LOW_4 (7'b1000000), + .TXGEARBOX_EN ("FALSE"), + .TXPCSRESET_TIME (5'b00001), + .TXPMARESET_TIME (5'b00001), + .TX_RXDETECT_CFG (14'h1832), + .TX_RXDETECT_REF (3'b100), + .CPLL_CFG (24'hBC07DC), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (5), + .CPLL_INIT_CFG (24'h00001E), + .CPLL_LOCK_CFG (16'h01E8), + .CPLL_REFCLK_DIV (1), + .RXOUT_DIV (RX_OUT_DIV), + .TXOUT_DIV (TX_OUT_DIV), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .RXDFELPMRESET_TIME (7'b0001111), + .RXLPM_HF_CFG (14'b00000011110000), + .RXLPM_LF_CFG (14'b00000011110000), + .RX_DFE_GAIN_CFG (23'h020FEA), + .RX_DFE_H2_CFG (12'b000000000000), + .RX_DFE_H3_CFG (12'b000001000000), + .RX_DFE_H4_CFG (11'b00011110000), + .RX_DFE_H5_CFG (11'b00011100000), + .RX_DFE_KL_CFG (13'b0000011111110), + .RX_DFE_LPM_CFG (16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DFE_UT_CFG (17'b10001111000000000), + .RX_DFE_VP_CFG (17'b00011111100000011), + .RX_CLKMUX_PD (1'b1), + .TX_CLKMUX_PD (1'b1), + .RX_INT_DATAWIDTH (1), + .TX_INT_DATAWIDTH (1), + .TX_QPI_STATUS_EN (1'b0), + .RX_DFE_KL_CFG2 (32'h3010D90C), + .RX_DFE_XYD_CFG (13'b0001100010000), + .TX_PREDRIVER_MODE (1'b0)) + i_gtxe2_channel ( + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'd1), + .CPLLPD (cpll_pd), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (cpll_rst), + .GTRSVD (16'b0000000000000000), + .PCSRSVDIN (16'b0000000000000000), + .PCSRSVDIN2 (5'b00000), + .PMARSVDIN (5'b00000), + .PMARSVDIN2 (5'b00000), + .TSTIN (20'b11111111111111111111), + .TSTOUT (), + .CLKRSVD (4'b0000), + .GTGREFCLK (1'd0), + .GTNORTHREFCLK0 (1'd0), + .GTNORTHREFCLK1 (1'd0), + .GTREFCLK0 (cpll_ref_clk_in), + .GTREFCLK1 (1'd0), + .GTSOUTHREFCLK0 (1'd0), + .GTSOUTHREFCLK1 (1'd0), + .DRPADDR (up_drp_addr[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_drp_wdata), + .DRPDO (up_drp_rdata), + .DRPEN (up_drp_sel), + .DRPRDY (up_drp_ready), + .DRPWE (up_drp_wr), + .GTREFCLKMONITOR (), + .QPLLCLK (qpll_clk), + .QPLLREFCLK (qpll_ref_clk), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .DMONITOROUT (), + .TX8B10BEN (1'd1), + .LOOPBACK (3'd0), + .PHYSTATUS (), + .RXRATE (rx_rate_p_s), + .RXVALID (), + .RXPD (2'b00), + .TXPD (2'b00), + .SETERRSTATUS (1'd0), + .EYESCANRESET (1'd0), + .RXUSERRDY (rx_user_ready), + .EYESCANDATAERROR (), + .EYESCANMODE (1'd0), + .EYESCANTRIGGER (1'd0), + .RXCDRFREQRESET (1'd0), + .RXCDRHOLD (1'd0), + .RXCDRLOCK (), + .RXCDROVRDEN (1'd0), + .RXCDRRESET (1'd0), + .RXCDRRESETRSV (1'd0), + .RXCLKCORCNT (), + .RX8B10BEN (1'd1), + .RXUSRCLK (rx_clk), + .RXUSRCLK2 (rx_clk), + .RXDATA ({rx_data_open_s, rx_gt_data}), + .RXPRBSERR (), + .RXPRBSSEL (3'd0), + .RXPRBSCNTRESET (1'd0), + .RXDFEXYDEN (1'd0), + .RXDFEXYDHOLD (1'd0), + .RXDFEXYDOVRDEN (1'd0), + .RXDISPERR ({rx_disperr_open_s, rx_gt_disperr}), + .RXNOTINTABLE ({rx_notintable_open_s, rx_gt_notintable}), + .GTXRXP (rx_p), + .GTXRXN (rx_n), + .RXBUFRESET (1'd0), + .RXBUFSTATUS (), + .RXDDIEN (1'd0), + .RXDLYBYPASS (1'd1), + .RXDLYEN (1'd0), + .RXDLYOVRDEN (1'd0), + .RXDLYSRESET (1'd0), + .RXDLYSRESETDONE (), + .RXPHALIGN (1'd0), + .RXPHALIGNDONE (), + .RXPHALIGNEN (1'd0), + .RXPHDLYPD (1'd0), + .RXPHDLYRESET (1'd0), + .RXPHMONITOR (), + .RXPHOVRDEN (1'd0), + .RXPHSLIPMONITOR (), + .RXSTATUS (), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCOMMADET (), + .RXCOMMADETEN (1'd1), + .RXMCOMMAALIGNEN (rx_gt_comma_align_enb), + .RXPCOMMAALIGNEN (rx_gt_comma_align_enb), + .RXCHANBONDSEQ (), + .RXCHBONDEN (1'd0), + .RXCHBONDLEVEL (3'd0), + .RXCHBONDMASTER (1'd1), + .RXCHBONDO (), + .RXCHBONDSLAVE (1'd0), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXDFEAGCHOLD (1'd0), + .RXDFEAGCOVRDEN (1'd0), + .RXDFECM1EN (1'd0), + .RXDFELFHOLD (1'd0), + .RXDFELFOVRDEN (1'd1), + .RXDFELPMRESET (1'd0), + .RXDFETAP2HOLD (1'd0), + .RXDFETAP2OVRDEN (1'd0), + .RXDFETAP3HOLD (1'd0), + .RXDFETAP3OVRDEN (1'd0), + .RXDFETAP4HOLD (1'd0), + .RXDFETAP4OVRDEN (1'd0), + .RXDFETAP5HOLD (1'd0), + .RXDFETAP5OVRDEN (1'd0), + .RXDFEUTHOLD (1'd0), + .RXDFEUTOVRDEN (1'd0), + .RXDFEVPHOLD (1'd0), + .RXDFEVPOVRDEN (1'd0), + .RXDFEVSEN (1'd0), + .RXLPMLFKLOVRDEN (1'd0), + .RXMONITOROUT (), + .RXMONITORSEL (2'd0), + .RXOSHOLD (1'd0), + .RXOSOVRDEN (1'd0), + .RXLPMHFHOLD (1'd0), + .RXLPMHFOVRDEN (1'd0), + .RXLPMLFHOLD (1'd0), + .RXRATEDONE (), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (rx_out_clk_sel), + .RXDATAVALID (), + .RXHEADER (), + .RXHEADERVALID (), + .RXSTARTOFSEQ (), + .RXGEARBOXSLIP (1'd0), + .GTRXRESET (rx_rst), + .RXOOBRESET (1'd0), + .RXPCSRESET (1'd0), + .RXPMARESET (1'd0), + .RXLPMEN (lpm_dfe_n), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCOMINITDET (), + .RXELECIDLE (), + .RXELECIDLEMODE (2'b10), + .RXPOLARITY (1'd0), + .RXSLIDE (1'd0), + .RXCHARISCOMMA (), + .RXCHARISK ({rx_charisk_open_s, rx_gt_charisk}), + .RXCHBONDI (5'd0), + .RXRESETDONE (rx_rst_done), + .RXQPIEN (1'd0), + .RXQPISENN (), + .RXQPISENP (), + .TXPHDLYTSTCLK (1'd0), + .TXPOSTCURSOR (5'd0), + .TXPOSTCURSORINV (1'd0), + .TXPRECURSOR (5'd0), + .TXPRECURSORINV (1'd0), + .TXQPIBIASEN (1'd0), + .TXQPISTRONGPDOWN (1'd0), + .TXQPIWEAKPUP (1'd0), + .CFGRESET (1'd0), + .GTTXRESET (tx_rst), + .PCSRSVDOUT (), + .TXUSERRDY (tx_user_ready), + .GTRESETSEL (1'd0), + .RESETOVRD (1'd0), + .TXCHARDISPMODE (8'd0), + .TXCHARDISPVAL (8'd0), + .TXUSRCLK (tx_clk), + .TXUSRCLK2 (tx_clk), + .TXELECIDLE (1'd0), + .TXMARGIN (3'd0), + .TXRATE (3'd0), + .TXSWING (1'd0), + .TXPRBSFORCEERR (1'd0), + .TXDLYBYPASS (1'd1), + .TXDLYEN (1'd0), + .TXDLYHOLD (1'd0), + .TXDLYOVRDEN (1'd0), + .TXDLYSRESET (1'd0), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (1'd0), + .TXPHALIGN (1'd0), + .TXPHALIGNDONE (), + .TXPHALIGNEN (1'd0), + .TXPHDLYPD (1'd0), + .TXPHDLYRESET (1'd0), + .TXPHINIT (1'd0), + .TXPHINITDONE (), + .TXPHOVRDEN (1'd0), + .TXBUFSTATUS (), + .TXBUFDIFFCTRL (3'b100), + .TXDEEMPH (1'd0), + .TXDIFFCTRL (4'b1000), + .TXDIFFPD (1'd0), + .TXINHIBIT (1'd0), + .TXMAINCURSOR (7'b0000000), + .TXPISOPD (1'd0), + .TXDATA ({32'd0, tx_gt_data}), + .GTXTXP (tx_p), + .GTXTXN (tx_n), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (tx_out_clk_sel), + .TXRATEDONE (), + .TXCHARISK ({4'd0, tx_gt_charisk}), + .TXGEARBOXREADY (), + .TXHEADER (3'd0), + .TXSEQUENCE (7'd0), + .TXSTARTSEQ (1'd0), + .TXPCSRESET (1'd0), + .TXPMARESET (1'd0), + .TXRESETDONE (tx_rst_done), + .TXCOMFINISH (), + .TXCOMINIT (1'd0), + .TXCOMSAS (1'd0), + .TXCOMWAKE (1'd0), + .TXPDELECIDLEMODE (1'd0), + .TXPOLARITY (1'd0), + .TXDETECTRX (1'd0), + .TX8B10BBYPASS (8'd0), + .TXPRBSSEL (3'd0), + .TXQPISENP (), + .TXQPISENN ()); + end + + if (GTH_GTX_N == 1) begin + + assign rx_sys_clk_sel_s = (rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign tx_sys_clk_sel_s = (tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign rx_pll_clk_sel_s = rx_sys_clk_sel; + assign tx_pll_clk_sel_s = tx_sys_clk_sel; + + if (RX_CLKBUF_ENABLE == 1) begin + BUFG_GT i_bufg_rx_clk ( + .I (rx_out_clk_s), + .O (rx_out_clk)); + end + + if (TX_CLKBUF_ENABLE == 1) begin + BUFG_GT i_bufg_tx_clk ( + .I (tx_out_clk_s), + .O (tx_out_clk)); + end + + GTHE3_CHANNEL #( + .ACJTAG_DEBUG_MODE (1'b0), + .ACJTAG_MODE (1'b0), + .ACJTAG_RESET (1'b0), + .ADAPT_CFG0 (16'b1111100000000000), + .ADAPT_CFG1 (16'b0000000000000000), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .A_RXOSCALRESET (1'b0), + .A_RXPROGDIVRESET (1'b0), + .A_TXPROGDIVRESET (1'b0), + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CDR_SWAP_MODE_EN (1'b0), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0100000000), + .CLK_COR_SEQ_1_3 (10'b0100000000), + .CLK_COR_SEQ_1_4 (10'b0100000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0100000000), + .CLK_COR_SEQ_2_3 (10'b0100000000), + .CLK_COR_SEQ_2_4 (10'b0100000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG0 (16'b0110011111111010), + .CPLL_CFG1 (16'b1010010010010100), + .CPLL_CFG2 (16'b1111000000000111), + .CPLL_CFG3 (6'b000000), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (5), + .CPLL_INIT_CFG0 (16'b0000000000011110), + .CPLL_INIT_CFG1 (8'b00000000), + .CPLL_LOCK_CFG (16'b0000000111101000), + .CPLL_REFCLK_DIV (1), + .DDI_CTRL (2'b00), + .DDI_REALIGN_WAIT (15), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DFE_D_X_REL_POS (1'b0), + .DFE_VCM_COMP_EN (1'b0), + .DMONITOR_CFG0 (10'b0000000000), + .DMONITOR_CFG1 (8'b00000000), + .ES_CLK_PHASE_SEL (1'b0), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'b000000000000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER0 (16'b0000000000000000), + .ES_QUALIFIER1 (16'b0000000000000000), + .ES_QUALIFIER2 (16'b0000000000000000), + .ES_QUALIFIER3 (16'b0000000000000000), + .ES_QUALIFIER4 (16'b0000000000000000), + .ES_QUAL_MASK0 (16'b0000000000000000), + .ES_QUAL_MASK1 (16'b0000000000000000), + .ES_QUAL_MASK2 (16'b0000000000000000), + .ES_QUAL_MASK3 (16'b0000000000000000), + .ES_QUAL_MASK4 (16'b0000000000000000), + .ES_SDATA_MASK0 (16'b0000000000000000), + .ES_SDATA_MASK1 (16'b0000000000000000), + .ES_SDATA_MASK2 (16'b0000000000000000), + .ES_SDATA_MASK3 (16'b0000000000000000), + .ES_SDATA_MASK4 (16'b0000000000000000), + .EVODD_PHI_CFG (11'b00000000000), + .EYE_SCAN_SWAP_EN (1'b0), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (5'b00000), + .GM_BIAS_SELECT (1'b0), + .LOCAL_MASTER (1'b1), + .OOBDIVCTL (2'b00), + .OOB_PWRUP (1'b0), + .PCI3_AUTO_REALIGN ("OVR_1K_BLK"), + .PCI3_PIPE_RX_ELECIDLE (1'b0), + .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00), + .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0), + .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000), + .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0), + .PCI3_RX_FIFO_DISABLE (1'b0), + .PCIE_BUFG_DIV_CTRL (16'b0011010100001001), + .PCIE_RXPCS_CFG_GEN3 (16'b0000001010100100), + .PCIE_RXPMA_CFG (16'b0000000000001010), + .PCIE_TXPCS_CFG_GEN3 (16'b0010010010100000), + .PCIE_TXPMA_CFG (16'b0000000000001010), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD0 (16'b0000000000000000), + .PCS_RSVD1 (3'b000), + .PD_TRANS_TIME_FROM_P2 (12'b000000111100), + .PD_TRANS_TIME_NONE_P2 (8'b00011001), + .PD_TRANS_TIME_TO_P2 (8'b01100100), + .PLL_SEL_MODE_GEN12 (2'b11), + .PLL_SEL_MODE_GEN3 (2'b11), + .PMA_RSV1 (16'b0001000000000000), + .PROCESS_PAR (3'b010), + .RATE_SW_USE_DRP (1'b0), + .RESET_POWERSAVE_DISABLE (1'b0), + .RXBUFRESET_TIME (5'b00011), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("FALSE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (3), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG0 (16'b0000000000000000), + .RXCDR_CFG0_GEN3 (16'b0000000000000000), + .RXCDR_CFG1 (16'b0000000000000000), + .RXCDR_CFG1_GEN3 (16'b0000000000000000), + .RXCDR_CFG2 (16'b0000011101100110), + .RXCDR_CFG2_GEN3 (16'b0000011101100110), + .RXCDR_CFG3 (16'b0000000000000000), + .RXCDR_CFG3_GEN3 (16'b0000000000000000), + .RXCDR_CFG4 (16'b0000000000000000), + .RXCDR_CFG4_GEN3 (16'b0000000000000000), + .RXCDR_CFG5 (16'b0000000000000000), + .RXCDR_CFG5_GEN3 (16'b0000000000000000), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG0 (16'b0100010010000000), + .RXCDR_LOCK_CFG1 (16'b0101111111111111), + .RXCDR_LOCK_CFG2 (16'b0111011111000011), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCFOK_CFG0 (16'b0100000000000000), + .RXCFOK_CFG1 (16'b0000000001100101), + .RXCFOK_CFG2 (16'b0000000000101110), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDFELPM_KL_CFG0 (16'b0000000000000000), + .RXDFELPM_KL_CFG1 (16'b0000000000000010), + .RXDFELPM_KL_CFG2 (16'b0000000000000000), + .RXDFE_CFG0 (16'b0000101000000000), + .RXDFE_CFG1 (16'b0000000000000000), + .RXDFE_GC_CFG0 (16'b0000000000000000), + .RXDFE_GC_CFG1 (16'b0111100001100000), + .RXDFE_GC_CFG2 (16'b0000000000000000), + .RXDFE_H2_CFG0 (16'b0000000000000000), + .RXDFE_H2_CFG1 (16'b0000000000000000), + .RXDFE_H3_CFG0 (16'b0100000000000000), + .RXDFE_H3_CFG1 (16'b0000000000000000), + .RXDFE_H4_CFG0 (16'b0010000000000000), + .RXDFE_H4_CFG1 (16'b0000000000000011), + .RXDFE_H5_CFG0 (16'b0010000000000000), + .RXDFE_H5_CFG1 (16'b0000000000000011), + .RXDFE_H6_CFG0 (16'b0010000000000000), + .RXDFE_H6_CFG1 (16'b0000000000000000), + .RXDFE_H7_CFG0 (16'b0010000000000000), + .RXDFE_H7_CFG1 (16'b0000000000000000), + .RXDFE_H8_CFG0 (16'b0010000000000000), + .RXDFE_H8_CFG1 (16'b0000000000000000), + .RXDFE_H9_CFG0 (16'b0010000000000000), + .RXDFE_H9_CFG1 (16'b0000000000000000), + .RXDFE_HA_CFG0 (16'b0010000000000000), + .RXDFE_HA_CFG1 (16'b0000000000000000), + .RXDFE_HB_CFG0 (16'b0010000000000000), + .RXDFE_HB_CFG1 (16'b0000000000000000), + .RXDFE_HC_CFG0 (16'b0000000000000000), + .RXDFE_HC_CFG1 (16'b0000000000000000), + .RXDFE_HD_CFG0 (16'b0000000000000000), + .RXDFE_HD_CFG1 (16'b0000000000000000), + .RXDFE_HE_CFG0 (16'b0000000000000000), + .RXDFE_HE_CFG1 (16'b0000000000000000), + .RXDFE_HF_CFG0 (16'b0000000000000000), + .RXDFE_HF_CFG1 (16'b0000000000000000), + .RXDFE_OS_CFG0 (16'b1000000000000000), + .RXDFE_OS_CFG1 (16'b0000000000000000), + .RXDFE_UT_CFG0 (16'b1000000000000000), + .RXDFE_UT_CFG1 (16'b0000000000000011), + .RXDFE_VP_CFG0 (16'b1010101000000000), + .RXDFE_VP_CFG1 (16'b0000000000110011), + .RXDLY_CFG (16'b0000000000011111), + .RXDLY_LCFG (16'b0000000000110000), + .RXELECIDLE_CFG ("Sigcfg_4"), + .RXGBOX_FIFO_INIT_RD_ADDR (4), + .RXGEARBOX_EN ("FALSE"), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_CFG (16'b0000000000000000), + .RXLPM_GC_CFG (16'b0000000000000000), + .RXLPM_KH_CFG0 (16'b0000000000000000), + .RXLPM_KH_CFG1 (16'b0000000000000010), + .RXLPM_OS_CFG0 (16'b1000000000000000), + .RXLPM_OS_CFG1 (16'b0000000000000010), + .RXOOB_CFG (9'b000000110), + .RXOOB_CLK_CFG ("PMA"), + .RXOSCALRESET_TIME (5'b00011), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00011), + .RXPHBEACON_CFG (16'b0000000000000000), + .RXPHDLY_CFG (16'b0010000000100000), + .RXPHSAMP_CFG (16'b0010000100000000), + .RXPHSLIP_CFG (16'b0110011000100010), + .RXPH_MONITOR_SEL (5'b00000), + .RXPI_CFG0 (2'b00), + .RXPI_CFG1 (2'b00), + .RXPI_CFG2 (2'b00), + .RXPI_CFG3 (2'b00), + .RXPI_CFG4 (1'b0), + .RXPI_CFG5 (1'b1), + .RXPI_CFG6 (3'b000), + .RXPI_LPM (1'b0), + .RXPI_VREFSEL (1'b0), + .RXPMACLK_SEL ("DATA"), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXPRBS_LINKACQ_CNT (15), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RXSYNC_MULTILANE (1'b1), + .RXSYNC_OVRD (1'b0), + .RXSYNC_SKIP_DA (1'b0), + .RX_AFE_CM_EN (1'b0), + .RX_BIAS_CFG0 (16'b0000101010110100), + .RX_BUFFER_CFG (6'b000000), + .RX_CAPFF_SARC_ENB (1'b0), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (1'b1), + .RX_CLK_SLIP_OVRD (5'b00000), + .RX_CM_BUF_CFG (4'b1010), + .RX_CM_BUF_PD (1'b0), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (4'b1010), + .RX_CTLE3_LPF (8'b00000001), + .RX_DATA_WIDTH (40), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DFELPM_CFG0 (4'b0110), + .RX_DFELPM_CFG1 (1'b1), + .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), + .RX_DFE_AGC_CFG0 (2'b10), + .RX_DFE_AGC_CFG1 (3'b100), + .RX_DFE_KL_LPM_KH_CFG0 (2'b01), + .RX_DFE_KL_LPM_KH_CFG1 (3'b100), + .RX_DFE_KL_LPM_KL_CFG0 (2'b01), + .RX_DFE_KL_LPM_KL_CFG1 (3'b100), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_DIVRESET_TIME (5'b00001), + .RX_EN_HI_LR (1'b1), + .RX_EYESCAN_VS_CODE (7'b0000000), + .RX_EYESCAN_VS_NEG_DIR (1'b0), + .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_UT_SIGN (1'b0), + .RX_FABINT_USRCLK_FLOP (1'b0), + .RX_INT_DATAWIDTH (1), + .RX_PMA_POWER_SAVE (1'b0), + .RX_PROGDIV_CFG (20.0), + .RX_SAMPLE_PERIOD (3'b101), + .RX_SIG_VALID_DLY (11), + .RX_SUM_DFETAPREP_EN (1'b0), + .RX_SUM_IREF_TUNE (4'b0000), + .RX_SUM_RES_CTRL (2'b00), + .RX_SUM_VCMTUNE (4'b0000), + .RX_SUM_VCM_OVWR (1'b0), + .RX_SUM_VREF_TUNE (3'b000), + .RX_TUNE_AFE_OS (2'b10), + .RX_WIDEMODE_CDR (1'b1), + .RX_XCLK_SEL ("RXDES"), + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL (1'b0), + .SIM_VERSION (2), + .TAPDLY_SET_TX (2'b00), + .TEMPERATUR_PAR (4'b0010), + .TERM_RCAL_CFG (15'b100001000010000), + .TERM_RCAL_OVRD (3'b000), + .TRANS_TIME_RATE (8'b00001110), + .TST_RSV0 (8'b00000000), + .TST_RSV1 (8'b00000000), + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'b0000000000001001), + .TXDLY_LCFG (16'b0000000001010000), + .TXDRVBIAS_N (4'b1010), + .TXDRVBIAS_P (4'b1010), + .TXFIFO_ADDR_CFG ("LOW"), + .TXGBOX_FIFO_INIT_RD_ADDR (4), + .TXGEARBOX_EN ("FALSE"), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00011), + .TXPHDLY_CFG0 (16'b0010000000100000), + .TXPHDLY_CFG1 (16'b0000000011010101), + .TXPH_CFG (16'b0000100110000000), + .TXPH_MONITOR_SEL (5'b00000), + .TXPI_CFG0 (2'b00), + .TXPI_CFG1 (2'b00), + .TXPI_CFG2 (2'b00), + .TXPI_CFG3 (1'b0), + .TXPI_CFG4 (1'b1), + .TXPI_CFG5 (3'b000), + .TXPI_GRAY_SEL (1'b0), + .TXPI_INVSTROBE_SEL (1'b0), + .TXPI_LPM (1'b0), + .TXPI_PPMCLK_SEL ("TXUSRCLK2"), + .TXPI_PPM_CFG (8'b00000000), + .TXPI_SYNFREQ_PPM (3'b000), + .TXPI_VREFSEL (1'b0), + .TXPMARESET_TIME (5'b00011), + .TXSYNC_MULTILANE (1'b1), + .TXSYNC_OVRD (1'b0), + .TXSYNC_SKIP_DA (1'b0), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (1'b1), + .TX_DATA_WIDTH (40), + .TX_DCD_CFG (6'b000010), + .TX_DCD_EN (1'b0), + .TX_DEEMPH0 (6'b000000), + .TX_DEEMPH1 (6'b000000), + .TX_DIVRESET_TIME (5'b00001), + .TX_DRIVE_MODE ("DIRECT"), + .TX_EIDLE_ASSERT_DELAY (3'b100), + .TX_EIDLE_DEASSERT_DELAY (3'b011), + .TX_EML_PHI_TUNE (1'b0), + .TX_FABINT_USRCLK_FLOP (1'b0), + .TX_IDLE_DATA_ZERO (1'b0), + .TX_INT_DATAWIDTH (1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1001111), + .TX_MARGIN_FULL_1 (7'b1001110), + .TX_MARGIN_FULL_2 (7'b1001100), + .TX_MARGIN_FULL_3 (7'b1001010), + .TX_MARGIN_FULL_4 (7'b1001000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000101), + .TX_MARGIN_LOW_2 (7'b1000011), + .TX_MARGIN_LOW_3 (7'b1000010), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_MODE_SEL (3'b000), + .TX_PMADATA_OPT (1'b0), + .TX_PMA_POWER_SAVE (1'b0), + .TX_PROGCLK_SEL ("PREPI"), + .TX_PROGDIV_CFG (20.0), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'b00000000110010), + .TX_RXDETECT_REF (3'b100), + .TX_SAMPLE_PERIOD (3'b101), + .TX_SARC_LPBK_ENB (1'b0), + .TX_XCLK_SEL ("TXOUT"), + .USE_PCS_CLK_PHASE_SEL (1'b0), + .WB_MODE (2'b00)) + i_gthe3_channel ( + .CFGRESET (1'd0), + .CLKRSVD0 (1'd0), + .CLKRSVD1 (1'd0), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'd1), + .CPLLPD (cpll_pd), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (cpll_rst), + .DMONFIFORESET (1'd0), + .DMONITORCLK (1'd0), + .DRPADDR (up_drp_addr[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_drp_wdata), + .DRPEN (up_drp_sel), + .DRPWE (up_drp_wr), + .EVODDPHICALDONE (1'd0), + .EVODDPHICALSTART (1'd0), + .EVODDPHIDRDEN (1'd0), + .EVODDPHIDWREN (1'd0), + .EVODDPHIXRDEN (1'd0), + .EVODDPHIXWREN (1'd0), + .EYESCANMODE (1'd0), + .EYESCANRESET (1'd0), + .EYESCANTRIGGER (1'd0), + .GTGREFCLK (1'd0), + .GTHRXN (rx_n), + .GTHRXP (rx_p), + .GTNORTHREFCLK0 (1'd0), + .GTNORTHREFCLK1 (1'd0), + .GTREFCLK0 (cpll_ref_clk_in), + .GTREFCLK1 (1'd0), + .GTRESETSEL (1'd0), + .GTRSVD (15'd0), + .GTRXRESET (rx_rst), + .GTSOUTHREFCLK0 (1'd0), + .GTSOUTHREFCLK1 (1'd0), + .GTTXRESET (tx_rst), + .LOOPBACK (3'd0), + .LPBKRXTXSEREN (1'd0), + .LPBKTXRXSEREN (1'd0), + .PCIEEQRXEQADAPTDONE (1'd0), + .PCIERSTIDLE (1'd0), + .PCIERSTTXSYNCSTART (1'd0), + .PCIEUSERRATEDONE (1'd0), + .PCSRSVDIN (16'd0), + .PCSRSVDIN2 (5'd0), + .PMARSVDIN (5'd0), + .QPLL0CLK (qpll_clk), + .QPLL0REFCLK (qpll_ref_clk), + .QPLL1CLK (1'd0), + .QPLL1REFCLK (1'd0), + .RESETOVRD (1'd0), + .RSTCLKENTX (1'd0), + .RXBUFRESET (1'd0), + .RXCDRFREQRESET (1'd0), + .RXCDRHOLD (1'd0), + .RXCDROVRDEN (1'd0), + .RXCDRRESET (1'd0), + .RXCDRRESETRSV (1'd0), + .RXCHBONDEN (1'd0), + .RXCHBONDI (5'd0), + .RXCHBONDLEVEL (2'd0), + .RXCHBONDMASTER (1'd0), + .RXCHBONDSLAVE (1'd0), + .RXCOMMADETEN (1'd1), + .RXDFEAGCCTRL (2'b01), + .RXDFEAGCHOLD (1'd0), + .RXDFEAGCOVRDEN (1'd0), + .RXDFELFHOLD (1'd0), + .RXDFELFOVRDEN (1'd0), + .RXDFELPMRESET (1'd0), + .RXDFETAP10HOLD (1'd0), + .RXDFETAP10OVRDEN (1'd0), + .RXDFETAP11HOLD (1'd0), + .RXDFETAP11OVRDEN (1'd0), + .RXDFETAP12HOLD (1'd0), + .RXDFETAP12OVRDEN (1'd0), + .RXDFETAP13HOLD (1'd0), + .RXDFETAP13OVRDEN (1'd0), + .RXDFETAP14HOLD (1'd0), + .RXDFETAP14OVRDEN (1'd0), + .RXDFETAP15HOLD (1'd0), + .RXDFETAP15OVRDEN (1'd0), + .RXDFETAP2HOLD (1'd0), + .RXDFETAP2OVRDEN (1'd0), + .RXDFETAP3HOLD (1'd0), + .RXDFETAP3OVRDEN (1'd0), + .RXDFETAP4HOLD (1'd0), + .RXDFETAP4OVRDEN (1'd0), + .RXDFETAP5HOLD (1'd0), + .RXDFETAP5OVRDEN (1'd0), + .RXDFETAP6HOLD (1'd0), + .RXDFETAP6OVRDEN (1'd0), + .RXDFETAP7HOLD (1'd0), + .RXDFETAP7OVRDEN (1'd0), + .RXDFETAP8HOLD (1'd0), + .RXDFETAP8OVRDEN (1'd0), + .RXDFETAP9HOLD (1'd0), + .RXDFETAP9OVRDEN (1'd0), + .RXDFEUTHOLD (1'd0), + .RXDFEUTOVRDEN (1'd0), + .RXDFEVPHOLD (1'd0), + .RXDFEVPOVRDEN (1'd0), + .RXDFEVSEN (1'd0), + .RXDFEXYDEN (1'd1), + .RXDLYBYPASS (1'd1), + .RXDLYEN (1'd0), + .RXDLYOVRDEN (1'd0), + .RXDLYSRESET (1'd0), + .RXELECIDLEMODE (2'b11), + .RXGEARBOXSLIP (1'd0), + .RXLATCLK (1'd0), + .RXLPMEN (lpm_dfe_n), + .RXLPMGCHOLD (1'd0), + .RXLPMGCOVRDEN (1'd0), + .RXLPMHFHOLD (1'd0), + .RXLPMHFOVRDEN (1'd0), + .RXLPMLFHOLD (1'd0), + .RXLPMLFKLOVRDEN (1'd0), + .RXLPMOSHOLD (1'd0), + .RXLPMOSOVRDEN (1'd0), + .RXMCOMMAALIGNEN (rx_gt_comma_align_enb), + .RXMONITORSEL (2'd0), + .RXOOBRESET (1'd0), + .RXOSCALRESET (1'd0), + .RXOSHOLD (1'd0), + .RXOSINTCFG (4'b1101), + .RXOSINTEN (1'd1), + .RXOSINTHOLD (1'd0), + .RXOSINTOVRDEN (1'd0), + .RXOSINTSTROBE (1'd0), + .RXOSINTTESTOVRDEN (1'd0), + .RXOSOVRDEN (1'd0), + .RXOUTCLKSEL (rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_gt_comma_align_enb), + .RXPCSRESET (1'd0), + .RXPD (2'd0), + .RXPHALIGN (1'd0), + .RXPHALIGNEN (1'd0), + .RXPHDLYPD (1'd1), + .RXPHDLYRESET (1'd0), + .RXPHOVRDEN (1'd0), + .RXPLLCLKSEL (rx_pll_clk_sel_s), + .RXPMARESET (1'd0), + .RXPOLARITY (1'd0), + .RXPRBSCNTRESET (1'd0), + .RXPRBSSEL (4'd0), + .RXPROGDIVRESET (1'd0), + .RXQPIEN (1'd0), + .RXRATE (rx_rate_p_s), + .RXRATEMODE (1'd0), + .RXSLIDE (1'd0), + .RXSLIPOUTCLK (1'd0), + .RXSLIPPMA (1'd0), + .RXSYNCALLIN (1'd0), + .RXSYNCIN (1'd0), + .RXSYNCMODE (1'd0), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXUSERRDY (rx_user_ready), + .RXUSRCLK (rx_clk), + .RXUSRCLK2 (rx_clk), + .RX8B10BEN (1'd1), + .SIGVALIDCLK (1'd0), + .TSTIN (20'd0), + .TXBUFDIFFCTRL (3'd0), + .TXCOMINIT (1'd0), + .TXCOMSAS (1'd0), + .TXCOMWAKE (1'd0), + .TXCTRL0 (16'd0), + .TXCTRL1 (16'd0), + .TXCTRL2 ({4'd0, tx_gt_charisk}), + .TXDATA ({32'd0, tx_gt_data}), + .TXDATAEXTENDRSVD (8'd0), + .TXDEEMPH (1'd0), + .TXDETECTRX (1'd0), + .TXDIFFCTRL (4'b1100), + .TXDIFFPD (1'd0), + .TXDLYBYPASS (1'd1), + .TXDLYEN (1'd0), + .TXDLYHOLD (1'd0), + .TXDLYOVRDEN (1'd0), + .TXDLYSRESET (1'd0), + .TXDLYUPDOWN (1'd0), + .TXELECIDLE (1'd0), + .TXHEADER (6'd0), + .TXINHIBIT (1'd0), + .TXLATCLK (1'd0), + .TXMAINCURSOR (7'b1000000), + .TXMARGIN (3'd0), + .TXOUTCLKSEL (tx_out_clk_sel), + .TXPCSRESET (1'd0), + .TXPD (2'd0), + .TXPDELECIDLEMODE (1'd0), + .TXPHALIGN (1'd0), + .TXPHALIGNEN (1'd0), + .TXPHDLYPD (1'd1), + .TXPHDLYRESET (1'd0), + .TXPHDLYTSTCLK (1'd0), + .TXPHINIT (1'd0), + .TXPHOVRDEN (1'd0), + .TXPIPPMEN (1'd0), + .TXPIPPMOVRDEN (1'd0), + .TXPIPPMPD (1'd0), + .TXPIPPMSEL (1'd0), + .TXPIPPMSTEPSIZE (5'd0), + .TXPISOPD (1'd0), + .TXPLLCLKSEL (tx_pll_clk_sel_s), + .TXPMARESET (1'd0), + .TXPOLARITY (1'd0), + .TXPOSTCURSOR (5'd0), + .TXPOSTCURSORINV (1'd0), + .TXPRBSFORCEERR (1'd0), + .TXPRBSSEL (4'd0), + .TXPRECURSOR (5'd0), + .TXPRECURSORINV (1'd0), + .TXPROGDIVRESET (tx_rst), + .TXQPIBIASEN (1'd0), + .TXQPISTRONGPDOWN (1'd0), + .TXQPIWEAKPUP (1'd0), + .TXRATE (3'd0), + .TXRATEMODE (1'd0), + .TXSEQUENCE (7'd0), + .TXSWING (1'd0), + .TXSYNCALLIN (1'd0), + .TXSYNCIN (1'd0), + .TXSYNCMODE (1'd0), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (tx_user_ready), + .TXUSRCLK (tx_clk), + .TXUSRCLK2 (tx_clk), + .TX8B10BBYPASS (8'd0), + .TX8B10BEN (1'd1), + .BUFGTCE (), + .BUFGTCEMASK (), + .BUFGTDIV (), + .BUFGTRESET (), + .BUFGTRSTMASK (), + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLREFCLKLOST (), + .DMONITOROUT (), + .DRPDO (up_drp_rdata), + .DRPRDY (up_drp_ready), + .EYESCANDATAERROR (), + .GTHTXN (tx_n), + .GTHTXP (tx_p), + .GTPOWERGOOD (), + .GTREFCLKMONITOR (), + .PCIERATEGEN3 (), + .PCIERATEIDLE (), + .PCIERATEQPLLPD (), + .PCIERATEQPLLRESET (), + .PCIESYNCTXSYNCDONE (), + .PCIEUSERGEN3RDY (), + .PCIEUSERPHYSTATUSRST (), + .PCIEUSERRATESTART (), + .PCSRSVDOUT (), + .PHYSTATUS (), + .PINRSRVDAS (), + .RESETEXCEPTION (), + .RXBUFSTATUS (), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRLOCK (), + .RXCDRPHDONE (), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCHBONDO (), + .RXCLKCORCNT (), + .RXCOMINITDET (), + .RXCOMMADET (), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCTRL0 ({rx_charisk_open_s, rx_gt_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_gt_disperr}), + .RXCTRL2 (), + .RXCTRL3 ({rx_notintable_open_s, rx_gt_notintable}), + .RXDATA ({rx_data_open_s, rx_gt_data}), + .RXDATAEXTENDRSVD (), + .RXDATAVALID (), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXHEADER (), + .RXHEADERVALID (), + .RXMONITOROUT (), + .RXOSINTDONE (), + .RXOSINTSTARTED (), + .RXOSINTSTROBEDONE (), + .RXOSINTSTROBESTARTED (), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXPHALIGNDONE (), + .RXPHALIGNERR (), + .RXPMARESETDONE (), + .RXPRBSERR (), + .RXPRBSLOCKED (), + .RXPRGDIVRESETDONE (), + .RXQPISENN (), + .RXQPISENP (), + .RXRATEDONE (), + .RXRECCLKOUT (), + .RXRESETDONE (rx_rst_done), + .RXSLIDERDY (), + .RXSLIPDONE (), + .RXSLIPOUTCLKRDY (), + .RXSLIPPMARDY (), + .RXSTARTOFSEQ (), + .RXSTATUS (), + .RXSYNCDONE (), + .RXSYNCOUT (), + .RXVALID (), + .TXBUFSTATUS (), + .TXCOMFINISH (), + .TXDLYSRESETDONE (), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXPHALIGNDONE (), + .TXPHINITDONE (), + .TXPMARESETDONE (), + .TXPRGDIVRESETDONE (), + .TXQPISENN (), + .TXQPISENP (), + .TXRATEDONE (), + .TXRESETDONE (tx_rst_done), + .TXSYNCDONE (), + .TXSYNCOUT ()); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/common/ad_gt_common.v b/library/common/ad_gt_common.v new file mode 100644 index 000000000..23993407d --- /dev/null +++ b/library/common/ad_gt_common.v @@ -0,0 +1,306 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module ad_gt_common ( + + // reset and clocks + + qpll_ref_clk_in, + qpll_rst, + qpll_clk, + qpll_ref_clk, + qpll_locked, + + // drp interface + + up_clk, + up_drp_sel, + up_drp_addr, + up_drp_wr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready); + + // parameters + + parameter integer GTH_GTX_N = 0; + parameter integer QPLL_ENABLE = 1; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [26:0] QPLL_CFG = 27'h06801C1; + parameter integer QPLL_FBDIV_RATIO = 1'b1; + parameter [ 9:0] QPLL_FBDIV = 10'b0000110000; + + // reset and clocks + + input qpll_ref_clk_in; + input qpll_rst; + output qpll_clk; + output qpll_ref_clk; + output qpll_locked; + + // drp interface + + input up_clk; + input up_drp_sel; + input [11:0] up_drp_addr; + input up_drp_wr; + input [15:0] up_drp_wdata; + output [15:0] up_drp_rdata; + output up_drp_ready; + + // instantiations + + generate + + if (QPLL_ENABLE == 0) begin + assign qpll_clk = 1'd0; + assign qpll_ref_clk = 1'd0; + assign qpll_locked = 1'd0; + assign up_drp_rdata = 16'd0; + assign up_drp_ready = 1'd0; + end + + if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 0)) begin + GTXE2_COMMON #( + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("3.0"), + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (QPLL_CFG), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV)) + i_gtxe2_common ( + .DRPCLK (up_clk), + .DRPEN (up_drp_sel), + .DRPADDR (up_drp_addr[7:0]), + .DRPWE (up_drp_wr), + .DRPDI (up_drp_wdata), + .DRPDO (up_drp_rdata), + .DRPRDY (up_drp_ready), + .GTGREFCLK (1'd0), + .GTNORTHREFCLK0 (1'd0), + .GTNORTHREFCLK1 (1'd0), + .GTREFCLK0 (qpll_ref_clk_in), + .GTREFCLK1 (1'd0), + .GTSOUTHREFCLK0 (1'd0), + .GTSOUTHREFCLK1 (1'd0), + .QPLLDMONITOR (), + .QPLLOUTCLK (qpll_clk), + .QPLLOUTREFCLK (qpll_ref_clk), + .REFCLKOUTMONITOR (), + .QPLLFBCLKLOST (), + .QPLLLOCK (qpll_locked), + .QPLLLOCKDETCLK (up_clk), + .QPLLLOCKEN (1'd1), + .QPLLOUTRESET (1'd0), + .QPLLPD (1'd0), + .QPLLREFCLKLOST (), + .QPLLREFCLKSEL (3'b001), + .QPLLRESET (qpll_rst), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + .BGBYPASSB (1'd1), + .BGMONITORENB (1'd1), + .BGPDB (1'd1), + .BGRCALOVRD (5'b00000), + .PMARSVD (8'b00000000), + .RCALENB (1'd1)); + end + + if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 1)) begin + GTHE3_COMMON #( + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_VERSION (2), + .SARC_EN (1'b1), + .SARC_SEL (1'b0), + .SDM0_DATA_PIN_SEL (1'b0), + .SDM0_WIDTH_PIN_SEL (1'b0), + .SDM1_DATA_PIN_SEL (1'b0), + .SDM1_WIDTH_PIN_SEL (1'b0), + .BIAS_CFG0 (16'b0000000000000000), + .BIAS_CFG1 (16'b0000000000000000), + .BIAS_CFG2 (16'b0000000000000000), + .BIAS_CFG3 (16'b0000000001000000), + .BIAS_CFG4 (16'b0000000000000000), + .COMMON_CFG0 (16'b0000000000000000), + .COMMON_CFG1 (16'b0000000000000000), + .POR_CFG (16'b0000000000000100), + .QPLL0_CFG0 (16'b0011000000011100), + .QPLL0_CFG1 (16'b0000000000011000), + .QPLL0_CFG1_G3 (16'b0000000000011000), + .QPLL0_CFG2 (16'b0000000001001000), + .QPLL0_CFG2_G3 (16'b0000000001001000), + .QPLL0_CFG3 (16'b0000000100100000), + .QPLL0_CFG4 (16'b0000000000001001), + .QPLL0_INIT_CFG0 (16'b0000000000000000), + .QPLL0_LOCK_CFG (16'b0010010111101000), + .QPLL0_LOCK_CFG_G3 (16'b0010010111101000), + .QPLL0_SDM_CFG0 (16'b0000000000000000), + .QPLL0_SDM_CFG1 (16'b0000000000000000), + .QPLL0_SDM_CFG2 (16'b0000000000000000), + .QPLL1_CFG0 (16'b0011000000011100), + .QPLL1_CFG1 (16'b0000000000011000), + .QPLL1_CFG1_G3 (16'b0000000000011000), + .QPLL1_CFG2 (16'b0000000001000000), + .QPLL1_CFG2_G3 (16'b0000000001000000), + .QPLL1_CFG3 (16'b0000000100100000), + .QPLL1_CFG4 (16'b0000000000001001), + .QPLL1_INIT_CFG0 (16'b0000000000000000), + .QPLL1_LOCK_CFG (16'b0010010111101000), + .QPLL1_LOCK_CFG_G3 (16'b0010010111101000), + .QPLL1_SDM_CFG0 (16'b0000000000000000), + .QPLL1_SDM_CFG1 (16'b0000000000000000), + .QPLL1_SDM_CFG2 (16'b0000000000000000), + .RSVD_ATTR0 (16'b0000000000000000), + .RSVD_ATTR1 (16'b0000000000000000), + .RSVD_ATTR2 (16'b0000000000000000), + .RSVD_ATTR3 (16'b0000000000000000), + .SDM0DATA1_0 (16'b0000000000000000), + .SDM0INITSEED0_0 (16'b0000000000000000), + .SDM1DATA1_0 (16'b0000000000000000), + .SDM1INITSEED0_0 (16'b0000000000000000), + .RXRECCLKOUT0_SEL (2'b00), + .RXRECCLKOUT1_SEL (2'b00), + .QPLL0_INIT_CFG1 (8'b00000000), + .QPLL1_INIT_CFG1 (8'b00000000), + .SDM0DATA1_1 (9'b000000000), + .SDM0INITSEED0_1 (9'b000000000), + .SDM1DATA1_1 (9'b000000000), + .SDM1INITSEED0_1 (9'b000000000), + .BIAS_CFG_RSVD (10'b0000000000), + .QPLL0_CP (10'b0000011111), + .QPLL0_CP_G3 (10'b1111111111), + .QPLL0_LPF (10'b1111111111), + .QPLL0_LPF_G3 (10'b0000010101), + .QPLL1_CP (10'b0000011111), + .QPLL1_CP_G3 (10'b1111111111), + .QPLL1_LPF (10'b1111111111), + .QPLL1_LPF_G3 (10'b0000010101), + .QPLL0_FBDIV (QPLL_FBDIV), + .QPLL0_FBDIV_G3 (80), + .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL1_FBDIV (QPLL_FBDIV), + .QPLL1_FBDIV_G3 (80), + .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV)) + i_gthe3_common ( + .BGBYPASSB (1'd1), + .BGMONITORENB (1'd1), + .BGPDB (1'd1), + .BGRCALOVRD (5'b11111), + .BGRCALOVRDENB (1'd1), + .DRPADDR (up_drp_addr[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_drp_wdata), + .DRPEN (up_drp_sel), + .DRPWE (up_drp_wr), + .GTGREFCLK0 (1'd0), + .GTGREFCLK1 (1'd0), + .GTNORTHREFCLK00 (1'd0), + .GTNORTHREFCLK01 (1'd0), + .GTNORTHREFCLK10 (1'd0), + .GTNORTHREFCLK11 (1'd0), + .GTREFCLK00 (qpll_ref_clk_in), + .GTREFCLK01 (1'd0), + .GTREFCLK10 (1'd0), + .GTREFCLK11 (1'd0), + .GTSOUTHREFCLK00 (1'd0), + .GTSOUTHREFCLK01 (1'd0), + .GTSOUTHREFCLK10 (1'd0), + .GTSOUTHREFCLK11 (1'd0), + .PMARSVD0 (8'd0), + .PMARSVD1 (8'd0), + .QPLLRSVD1 (8'd0), + .QPLLRSVD2 (5'd0), + .QPLLRSVD3 (5'd0), + .QPLLRSVD4 (8'd0), + .QPLL0CLKRSVD0 (1'd0), + .QPLL0CLKRSVD1 (1'd0), + .QPLL0LOCKDETCLK (up_clk), + .QPLL0LOCKEN (1'd1), + .QPLL0PD (1'd0), + .QPLL0REFCLKSEL (3'b001), + .QPLL0RESET (qpll_rst), + .QPLL1CLKRSVD0 (1'd0), + .QPLL1CLKRSVD1 (1'd0), + .QPLL1LOCKDETCLK (1'd0), + .QPLL1LOCKEN (1'd0), + .QPLL1PD (1'd1), + .QPLL1REFCLKSEL (3'b001), + .QPLL1RESET (1'd1), + .RCALENB (1'd1), + .DRPDO (up_drp_rdata), + .DRPRDY (up_drp_ready), + .PMARSVDOUT0 (), + .PMARSVDOUT1 (), + .QPLLDMONITOR0 (), + .QPLLDMONITOR1 (), + .QPLL0FBCLKLOST (), + .QPLL0LOCK (qpll_locked), + .QPLL0OUTCLK (qpll_clk), + .QPLL0OUTREFCLK (qpll_ref_clk), + .QPLL0REFCLKLOST (), + .QPLL1FBCLKLOST (), + .QPLL1LOCK (), + .QPLL1OUTCLK (), + .QPLL1OUTREFCLK (), + .QPLL1REFCLKLOST (), + .REFCLKOUTMONITOR0 (), + .REFCLKOUTMONITOR1 (), + .RXRECCLK0_SEL (), + .RXRECCLK1_SEL ()); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/common/ad_gt_es_axi.v b/library/common/ad_gt_es_axi.v new file mode 100644 index 000000000..0fb54acc4 --- /dev/null +++ b/library/common/ad_gt_es_axi.v @@ -0,0 +1,457 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_gt_es_axi ( + + // es interface + + up_rstn, + up_clk, + up_es_dma_req_0, + up_es_dma_addr_0, + up_es_dma_data_0, + up_es_dma_ack_0, + up_es_dma_err_0, + up_es_dma_req_1, + up_es_dma_addr_1, + up_es_dma_data_1, + up_es_dma_ack_1, + up_es_dma_err_1, + up_es_dma_req_2, + up_es_dma_addr_2, + up_es_dma_data_2, + up_es_dma_ack_2, + up_es_dma_err_2, + up_es_dma_req_3, + up_es_dma_addr_3, + up_es_dma_data_3, + up_es_dma_ack_3, + up_es_dma_err_3, + up_es_dma_req_4, + up_es_dma_addr_4, + up_es_dma_data_4, + up_es_dma_ack_4, + up_es_dma_err_4, + up_es_dma_req_5, + up_es_dma_addr_5, + up_es_dma_data_5, + up_es_dma_ack_5, + up_es_dma_err_5, + up_es_dma_req_6, + up_es_dma_addr_6, + up_es_dma_data_6, + up_es_dma_ack_6, + up_es_dma_err_6, + up_es_dma_req_7, + up_es_dma_addr_7, + up_es_dma_data_7, + up_es_dma_ack_7, + up_es_dma_err_7, + + // axi4 interface + + axi_awvalid, + axi_awaddr, + axi_awprot, + axi_awready, + axi_wvalid, + axi_wdata, + axi_wstrb, + axi_wready, + axi_bvalid, + axi_bresp, + axi_bready, + axi_arvalid, + axi_araddr, + axi_arprot, + axi_arready, + axi_rvalid, + axi_rresp, + axi_rdata, + axi_rready); + + // state machine (fair RR?) + + localparam [ 3:0] AXI_FSM_SCAN_0 = 4'h0; + localparam [ 3:0] AXI_FSM_SCAN_1 = 4'h1; + localparam [ 3:0] AXI_FSM_SCAN_2 = 4'h2; + localparam [ 3:0] AXI_FSM_SCAN_3 = 4'h3; + localparam [ 3:0] AXI_FSM_SCAN_4 = 4'h4; + localparam [ 3:0] AXI_FSM_SCAN_5 = 4'h5; + localparam [ 3:0] AXI_FSM_SCAN_6 = 4'h6; + localparam [ 3:0] AXI_FSM_SCAN_7 = 4'h7; + localparam [ 3:0] AXI_FSM_WRITE = 4'h8; + localparam [ 3:0] AXI_FSM_WAIT = 4'h9; + localparam [ 3:0] AXI_FSM_ACK = 4'ha; + + // es interface + + input up_rstn; + input up_clk; + input up_es_dma_req_0; + input [31:0] up_es_dma_addr_0; + input [31:0] up_es_dma_data_0; + output up_es_dma_ack_0; + output up_es_dma_err_0; + input up_es_dma_req_1; + input [31:0] up_es_dma_addr_1; + input [31:0] up_es_dma_data_1; + output up_es_dma_ack_1; + output up_es_dma_err_1; + input up_es_dma_req_2; + input [31:0] up_es_dma_addr_2; + input [31:0] up_es_dma_data_2; + output up_es_dma_ack_2; + output up_es_dma_err_2; + input up_es_dma_req_3; + input [31:0] up_es_dma_addr_3; + input [31:0] up_es_dma_data_3; + output up_es_dma_ack_3; + output up_es_dma_err_3; + input up_es_dma_req_4; + input [31:0] up_es_dma_addr_4; + input [31:0] up_es_dma_data_4; + output up_es_dma_ack_4; + output up_es_dma_err_4; + input up_es_dma_req_5; + input [31:0] up_es_dma_addr_5; + input [31:0] up_es_dma_data_5; + output up_es_dma_ack_5; + output up_es_dma_err_5; + input up_es_dma_req_6; + input [31:0] up_es_dma_addr_6; + input [31:0] up_es_dma_data_6; + output up_es_dma_ack_6; + output up_es_dma_err_6; + input up_es_dma_req_7; + input [31:0] up_es_dma_addr_7; + input [31:0] up_es_dma_data_7; + output up_es_dma_ack_7; + output up_es_dma_err_7; + + // axi4 interface + + output axi_awvalid; + output [31:0] axi_awaddr; + output [ 2:0] axi_awprot; + input axi_awready; + output axi_wvalid; + output [31:0] axi_wdata; + output [ 3:0] axi_wstrb; + input axi_wready; + input axi_bvalid; + input [ 1:0] axi_bresp; + output axi_bready; + output axi_arvalid; + output [31:0] axi_araddr; + output [ 2:0] axi_arprot; + input axi_arready; + input axi_rvalid; + input [31:0] axi_rdata; + input [ 1:0] axi_rresp; + output axi_rready; + + // internal registers + + reg up_es_dma_ack_0 = 'd0; + reg up_es_dma_err_0 = 'd0; + reg up_es_dma_ack_1 = 'd0; + reg up_es_dma_err_1 = 'd0; + reg up_es_dma_ack_2 = 'd0; + reg up_es_dma_err_2 = 'd0; + reg up_es_dma_ack_3 = 'd0; + reg up_es_dma_err_3 = 'd0; + reg up_es_dma_ack_4 = 'd0; + reg up_es_dma_err_4 = 'd0; + reg up_es_dma_ack_5 = 'd0; + reg up_es_dma_err_5 = 'd0; + reg up_es_dma_ack_6 = 'd0; + reg up_es_dma_err_6 = 'd0; + reg up_es_dma_ack_7 = 'd0; + reg up_es_dma_err_7 = 'd0; + reg axi_awvalid = 'd0; + reg [31:0] axi_awaddr = 'd0; + reg axi_wvalid = 'd0; + reg [31:0] axi_wdata = 'd0; + reg axi_error = 'd0; + reg [ 2:0] axi_sel = 'd0; + reg [ 3:0] axi_fsm = 'd0; + + // axi write interface + + assign axi_awprot = 3'd0; + assign axi_wstrb = 4'hf; + assign axi_bready = 1'd1; + assign axi_arvalid = 1'd0; + assign axi_araddr = 32'd0; + assign axi_arprot = 3'd0; + assign axi_rready = 1'd1; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_es_dma_ack_0 <= 1'b0; + up_es_dma_err_0 <= 1'b0; + up_es_dma_ack_1 <= 1'b0; + up_es_dma_err_1 <= 1'b0; + up_es_dma_ack_2 <= 1'b0; + up_es_dma_err_2 <= 1'b0; + up_es_dma_ack_3 <= 1'b0; + up_es_dma_err_3 <= 1'b0; + up_es_dma_ack_4 <= 1'b0; + up_es_dma_err_4 <= 1'b0; + up_es_dma_ack_5 <= 1'b0; + up_es_dma_err_5 <= 1'b0; + up_es_dma_ack_6 <= 1'b0; + up_es_dma_err_6 <= 1'b0; + up_es_dma_ack_7 <= 1'b0; + up_es_dma_err_7 <= 1'b0; + end else begin + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd0)) begin + up_es_dma_ack_0 <= 1'b1; + up_es_dma_err_0 <= axi_error; + end else begin + up_es_dma_ack_0 <= 1'b0; + up_es_dma_err_0 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd1)) begin + up_es_dma_ack_1 <= 1'b1; + up_es_dma_err_1 <= axi_error; + end else begin + up_es_dma_ack_1 <= 1'b0; + up_es_dma_err_1 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd2)) begin + up_es_dma_ack_2 <= 1'b1; + up_es_dma_err_2 <= axi_error; + end else begin + up_es_dma_ack_2 <= 1'b0; + up_es_dma_err_2 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd3)) begin + up_es_dma_ack_3 <= 1'b1; + up_es_dma_err_3 <= axi_error; + end else begin + up_es_dma_ack_3 <= 1'b0; + up_es_dma_err_3 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd4)) begin + up_es_dma_ack_4 <= 1'b1; + up_es_dma_err_4 <= axi_error; + end else begin + up_es_dma_ack_4 <= 1'b0; + up_es_dma_err_4 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd5)) begin + up_es_dma_ack_5 <= 1'b1; + up_es_dma_err_5 <= axi_error; + end else begin + up_es_dma_ack_5 <= 1'b0; + up_es_dma_err_5 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd6)) begin + up_es_dma_ack_6 <= 1'b1; + up_es_dma_err_6 <= axi_error; + end else begin + up_es_dma_ack_6 <= 1'b0; + up_es_dma_err_6 <= 1'b0; + end + if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd7)) begin + up_es_dma_ack_7 <= 1'b1; + up_es_dma_err_7 <= axi_error; + end else begin + up_es_dma_ack_7 <= 1'b0; + up_es_dma_err_7 <= 1'b0; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + axi_awvalid <= 'b0; + axi_awaddr <= 'd0; + axi_wvalid <= 'b0; + axi_wdata <= 'd0; + axi_error <= 'd0; + end else begin + if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin + axi_awvalid <= 1'b0; + axi_awaddr <= 32'd0; + end else if (axi_fsm == AXI_FSM_WRITE) begin + axi_awvalid <= 1'b1; + case (axi_sel) + 3'b000: axi_awaddr <= up_es_dma_addr_0; + 3'b001: axi_awaddr <= up_es_dma_addr_1; + 3'b010: axi_awaddr <= up_es_dma_addr_2; + 3'b011: axi_awaddr <= up_es_dma_addr_3; + 3'b100: axi_awaddr <= up_es_dma_addr_4; + 3'b101: axi_awaddr <= up_es_dma_addr_5; + 3'b110: axi_awaddr <= up_es_dma_addr_6; + default: axi_awaddr <= up_es_dma_addr_7; + endcase + end + if ((axi_wvalid == 1'b1) && (axi_wready == 1'b1)) begin + axi_wvalid <= 1'b0; + axi_wdata <= 32'd0; + end else if (axi_fsm == AXI_FSM_WRITE) begin + axi_wvalid <= 1'b1; + case (axi_sel) + 3'b000: axi_wdata <= up_es_dma_data_0; + 3'b001: axi_wdata <= up_es_dma_data_1; + 3'b010: axi_wdata <= up_es_dma_data_2; + 3'b011: axi_wdata <= up_es_dma_data_3; + 3'b100: axi_wdata <= up_es_dma_data_4; + 3'b101: axi_wdata <= up_es_dma_data_5; + 3'b110: axi_wdata <= up_es_dma_data_6; + default: axi_wdata <= up_es_dma_data_7; + endcase + end + if (axi_bvalid == 1'b1) begin + axi_error <= axi_bresp[1] | axi_bresp[0]; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + axi_sel <= 3'd0; + axi_fsm <= AXI_FSM_SCAN_0; + end else begin + case (axi_fsm) + AXI_FSM_SCAN_0: begin + axi_sel <= 3'd0; + if (up_es_dma_req_0 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_1; + end + end + AXI_FSM_SCAN_1: begin + axi_sel <= 3'd1; + if (up_es_dma_req_1 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_2; + end + end + AXI_FSM_SCAN_2: begin + axi_sel <= 3'd2; + if (up_es_dma_req_2 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_3; + end + end + AXI_FSM_SCAN_3: begin + axi_sel <= 3'd3; + if (up_es_dma_req_3 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_4; + end + end + AXI_FSM_SCAN_4: begin + axi_sel <= 3'd4; + if (up_es_dma_req_4 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_5; + end + end + AXI_FSM_SCAN_5: begin + axi_sel <= 3'd5; + if (up_es_dma_req_5 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_6; + end + end + AXI_FSM_SCAN_6: begin + axi_sel <= 3'd6; + if (up_es_dma_req_6 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_7; + end + end + AXI_FSM_SCAN_7: begin + axi_sel <= 3'd7; + if (up_es_dma_req_7 == 1'b1) begin + axi_fsm <= AXI_FSM_WRITE; + end else begin + axi_fsm <= AXI_FSM_SCAN_0; + end + end + + AXI_FSM_WRITE: begin + axi_sel <= axi_sel; + axi_fsm <= AXI_FSM_WAIT; + end + AXI_FSM_WAIT: begin + axi_sel <= axi_sel; + if (axi_bvalid == 1'b1) begin + axi_fsm <= AXI_FSM_ACK; + end else begin + axi_fsm <= AXI_FSM_WAIT; + end + end + AXI_FSM_ACK: begin + axi_sel <= axi_sel; + case (axi_sel) + 3'b000: axi_fsm <= AXI_FSM_SCAN_1; + 3'b001: axi_fsm <= AXI_FSM_SCAN_2; + 3'b010: axi_fsm <= AXI_FSM_SCAN_3; + 3'b011: axi_fsm <= AXI_FSM_SCAN_4; + 3'b100: axi_fsm <= AXI_FSM_SCAN_5; + 3'b101: axi_fsm <= AXI_FSM_SCAN_6; + 3'b110: axi_fsm <= AXI_FSM_SCAN_7; + default: axi_fsm <= AXI_FSM_SCAN_0; + endcase + end + + default: begin + axi_fsm <= AXI_FSM_SCAN_0; + end + endcase + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/up_gt_channel.v b/library/common/up_gt_channel.v new file mode 100644 index 000000000..9f0a8d4fa --- /dev/null +++ b/library/common/up_gt_channel.v @@ -0,0 +1,806 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_gt_channel ( + + // gt interface + + pll_rst, + lpm_dfe_n, + cpll_pd, + + // receive interface + + rx_sys_clk_sel, + rx_out_clk_sel, + rx_clk, + rx_gt_rst, + rx_rst, + rx_rst_m, + rx_ip_rst, + rx_sysref, + rx_ip_sysref, + rx_ip_sync, + rx_sync, + rx_rst_done, + rx_rst_done_m, + rx_pll_locked, + rx_pll_locked_m, + rx_user_ready, + rx_ip_rst_done, + + // transmit interface + + tx_sys_clk_sel, + tx_out_clk_sel, + tx_clk, + tx_gt_rst, + tx_rst, + tx_rst_m, + tx_ip_rst, + tx_sysref, + tx_ip_sysref, + tx_sync, + tx_ip_sync, + tx_rst_done, + tx_rst_done_m, + tx_pll_locked, + tx_pll_locked_m, + tx_user_ready, + tx_ip_rst_done, + + // drp interface + + up_drp_sel, + up_drp_wr, + up_drp_addr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready, + up_drp_rxrate, + + // es interface + + up_es_drp_sel, + up_es_drp_wr, + up_es_drp_addr, + up_es_drp_wdata, + up_es_drp_rdata, + up_es_drp_ready, + up_es_start, + up_es_stop, + up_es_init, + up_es_prescale, + up_es_voffset_range, + up_es_voffset_step, + up_es_voffset_max, + up_es_voffset_min, + up_es_hoffset_max, + up_es_hoffset_min, + up_es_hoffset_step, + up_es_start_addr, + up_es_sdata0, + up_es_sdata1, + up_es_sdata2, + up_es_sdata3, + up_es_sdata4, + up_es_qdata0, + up_es_qdata1, + up_es_qdata2, + up_es_qdata3, + up_es_qdata4, + up_es_dma_err, + up_es_status, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter integer ID = 0; + parameter integer GTH_GTX_N = 0; + + // gt interface + + output pll_rst; + output lpm_dfe_n; + output cpll_pd; + + // receive interface + + output [ 1:0] rx_sys_clk_sel; + output [ 2:0] rx_out_clk_sel; + input rx_clk; + output rx_gt_rst; + output rx_rst; + input rx_rst_m; + output rx_ip_rst; + input rx_sysref; + output rx_ip_sysref; + input rx_ip_sync; + output rx_sync; + input rx_rst_done; + input rx_rst_done_m; + input rx_pll_locked; + input rx_pll_locked_m; + output rx_user_ready; + output rx_ip_rst_done; + + // transmit interface + + output [ 1:0] tx_sys_clk_sel; + output [ 2:0] tx_out_clk_sel; + input tx_clk; + output tx_gt_rst; + output tx_rst; + input tx_rst_m; + output tx_ip_rst; + input tx_sysref; + output tx_ip_sysref; + input tx_sync; + output tx_ip_sync; + input tx_rst_done; + input tx_rst_done_m; + input tx_pll_locked; + input tx_pll_locked_m; + output tx_user_ready; + output tx_ip_rst_done; + + // drp interface + + output up_drp_sel; + output up_drp_wr; + output [11:0] up_drp_addr; + output [15:0] up_drp_wdata; + input [15:0] up_drp_rdata; + input up_drp_ready; + input [ 7:0] up_drp_rxrate; + + // es interface + + input up_es_drp_sel; + input up_es_drp_wr; + input [11:0] up_es_drp_addr; + input [15:0] up_es_drp_wdata; + output [15:0] up_es_drp_rdata; + output up_es_drp_ready; + output up_es_start; + output up_es_stop; + output up_es_init; + output [ 4:0] up_es_prescale; + output [ 1:0] up_es_voffset_range; + output [ 7:0] up_es_voffset_step; + output [ 7:0] up_es_voffset_max; + output [ 7:0] up_es_voffset_min; + output [11:0] up_es_hoffset_max; + output [11:0] up_es_hoffset_min; + output [11:0] up_es_hoffset_step; + output [31:0] up_es_start_addr; + output [15:0] up_es_sdata0; + output [15:0] up_es_sdata1; + output [15:0] up_es_sdata2; + output [15:0] up_es_sdata3; + output [15:0] up_es_sdata4; + output [15:0] up_es_qdata0; + output [15:0] up_es_qdata1; + output [15:0] up_es_qdata2; + output [15:0] up_es_qdata3; + output [15:0] up_es_qdata4; + input up_es_dma_err; + input up_es_status; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg up_pll_preset = 'd1; + reg up_rx_gt_preset = 'd1; + reg up_rx_preset = 'd1; + reg up_tx_gt_preset = 'd1; + reg up_tx_preset = 'd1; + reg up_wack = 'd0; + reg up_lpm_dfe_n = 'd0; + reg up_cpll_pd = 'd0; + reg up_drp_resetn = 'd0; + reg up_pll_resetn = 'd0; + reg up_rx_gt_resetn = 'd0; + reg up_rx_resetn = 'd0; + reg [ 1:0] up_rx_sys_clk_sel = 'd0; + reg [ 2:0] up_rx_out_clk_sel = 'd0; + reg up_rx_sysref_sel = 'd0; + reg up_rx_sysref = 'd0; + reg up_rx_sync = 'd0; + reg up_rx_user_ready = 'd0; + reg up_tx_gt_resetn = 'd0; + reg up_tx_resetn = 'd0; + reg [ 1:0] up_tx_sys_clk_sel = 'd0; + reg [ 2:0] up_tx_out_clk_sel = 'd0; + reg up_tx_sysref_sel = 'd0; + reg up_tx_sysref = 'd0; + reg up_tx_sync = 'd0; + reg up_tx_user_ready = 'd0; + reg up_drp_sel_int = 'd0; + reg up_drp_wr_int = 'd0; + reg up_drp_status = 'd0; + reg up_drp_rwn = 'd0; + reg [11:0] up_drp_addr_int = 'd0; + reg [15:0] up_drp_wdata_int = 'd0; + reg [15:0] up_drp_rdata_hold = 'd0; + reg up_es_init = 'd0; + reg up_es_stop = 'd0; + reg up_es_stop_hold = 'd0; + reg up_es_start = 'd0; + reg up_es_start_hold = 'd0; + reg [ 4:0] up_es_prescale = 'd0; + reg [ 1:0] up_es_voffset_range = 'd0; + reg [ 7:0] up_es_voffset_step = 'd0; + reg [ 7:0] up_es_voffset_max = 'd0; + reg [ 7:0] up_es_voffset_min = 'd0; + reg [11:0] up_es_hoffset_max = 'd0; + reg [11:0] up_es_hoffset_min = 'd0; + reg [11:0] up_es_hoffset_step = 'd0; + reg [31:0] up_es_start_addr = 'd0; + reg [15:0] up_es_sdata1 = 'd0; + reg [15:0] up_es_sdata0 = 'd0; + reg [15:0] up_es_sdata3 = 'd0; + reg [15:0] up_es_sdata2 = 'd0; + reg [15:0] up_es_sdata4 = 'd0; + reg [15:0] up_es_qdata1 = 'd0; + reg [15:0] up_es_qdata0 = 'd0; + reg [15:0] up_es_qdata3 = 'd0; + reg [15:0] up_es_qdata2 = 'd0; + reg [15:0] up_es_qdata4 = 'd0; + reg up_es_dma_err_hold = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_rx_rst_done_m1 = 'd0; + reg up_rx_rst_done = 'd0; + reg up_rx_rst_done_m_m1 = 'd0; + reg up_rx_rst_done_m = 'd0; + reg up_rx_pll_locked_m1 = 'd0; + reg up_rx_pll_locked = 'd0; + reg up_rx_pll_locked_m_m1 = 'd0; + reg up_rx_pll_locked_m = 'd0; + reg up_rx_status_m1 = 'd0; + reg up_rx_status = 'd0; + reg up_tx_rst_done_m1 = 'd0; + reg up_tx_rst_done = 'd0; + reg up_tx_rst_done_m_m1 = 'd0; + reg up_tx_rst_done_m = 'd0; + reg up_tx_pll_locked_m1 = 'd0; + reg up_tx_pll_locked = 'd0; + reg up_tx_pll_locked_m_m1 = 'd0; + reg up_tx_pll_locked_m = 'd0; + reg up_tx_status_m1 = 'd0; + reg up_tx_status = 'd0; + reg up_drp_sel = 'd0; + reg up_drp_wr = 'd0; + reg [11:0] up_drp_addr = 'd0; + reg [15:0] up_drp_wdata = 'd0; + reg [15:0] up_es_drp_rdata = 'd0; + reg up_es_drp_ready = 'd0; + reg [15:0] up_drp_rdata_int = 'd0; + reg up_drp_ready_int = 'd0; + reg rx_sysref_sel_m1 = 'd0; + reg rx_sysref_sel = 'd0; + reg rx_up_sysref_m1 = 'd0; + reg rx_up_sysref = 'd0; + reg rx_ip_sysref = 'd0; + reg rx_up_sync_m1 = 'd0; + reg rx_up_sync = 'd0; + reg rx_sync = 'd0; + reg tx_sysref_sel_m1 = 'd0; + reg tx_sysref_sel = 'd0; + reg tx_up_sysref_m1 = 'd0; + reg tx_up_sysref = 'd0; + reg tx_ip_sysref = 'd0; + reg tx_up_sync_m1 = 'd0; + reg tx_up_sync = 'd0; + reg tx_ip_sync = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == ID) ? up_rreq : 1'b0; + + // user ready & ip reset done + + assign lpm_dfe_n = up_lpm_dfe_n; + assign cpll_pd = up_cpll_pd; + + assign rx_sys_clk_sel = up_rx_sys_clk_sel; + assign rx_out_clk_sel = up_rx_out_clk_sel; + assign rx_user_ready = up_rx_user_ready; + assign rx_ip_rst_done = up_rx_rst_done_m; + + assign tx_sys_clk_sel = up_tx_sys_clk_sel; + assign tx_out_clk_sel = up_tx_out_clk_sel; + assign tx_user_ready = up_tx_user_ready; + assign tx_ip_rst_done = up_tx_rst_done_m; + + // resets + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_pll_preset <= 1'b1; + up_rx_gt_preset <= 1'b1; + up_tx_gt_preset <= 1'b1; + up_rx_preset <= 1'b1; + up_tx_preset <= 1'b1; + end else begin + up_pll_preset <= ~up_pll_resetn; + up_rx_gt_preset <= ~(up_pll_resetn & + up_rx_pll_locked_m & up_rx_gt_resetn); + up_rx_preset <= ~(up_pll_resetn & up_rx_pll_locked_m & + up_rx_rst_done_m & up_rx_gt_resetn & up_rx_resetn); + up_tx_gt_preset <= ~(up_pll_resetn & + up_tx_pll_locked_m & up_tx_gt_resetn); + up_tx_preset <= ~(up_pll_resetn & up_tx_pll_locked_m & + up_tx_rst_done_m & up_tx_gt_resetn & up_tx_resetn); + end + end + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_lpm_dfe_n <= 'd0; + up_cpll_pd <= 'd1; + up_drp_resetn <= 'd0; + up_pll_resetn <= 'd0; + up_rx_gt_resetn <= 'd0; + up_rx_resetn <= 'd0; + up_rx_sys_clk_sel <= 2'b11; + up_rx_out_clk_sel <= 3'b010; + up_rx_sysref_sel <= 'd0; + up_rx_sysref <= 'd0; + up_rx_sync <= 'd0; + up_rx_user_ready <= 'd0; + up_tx_gt_resetn <= 'd0; + up_tx_resetn <= 'd0; + up_tx_sys_clk_sel <= 2'b11; + up_tx_out_clk_sel <= 3'b010; + up_tx_sysref_sel <= 'd0; + up_tx_sysref <= 'd0; + up_tx_sync <= 'd0; + up_tx_user_ready <= 'd0; + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold <= 'd0; + up_es_init <= 'd0; + up_es_stop <= 'd0; + up_es_stop_hold <= 'd0; + up_es_start <= 'd0; + up_es_start_hold <= 'd0; + up_es_prescale <= 'd0; + up_es_voffset_range <= 'd0; + up_es_voffset_step <= 'd0; + up_es_voffset_max <= 'd0; + up_es_voffset_min <= 'd0; + up_es_hoffset_max <= 'd0; + up_es_hoffset_min <= 'd0; + up_es_hoffset_step <= 'd0; + up_es_start_addr <= 'd0; + up_es_sdata1 <= 'd0; + up_es_sdata0 <= 'd0; + up_es_sdata3 <= 'd0; + up_es_sdata2 <= 'd0; + up_es_sdata4 <= 'd0; + up_es_qdata1 <= 'd0; + up_es_qdata0 <= 'd0; + up_es_qdata3 <= 'd0; + up_es_qdata2 <= 'd0; + up_es_qdata4 <= 'd0; + up_es_dma_err_hold <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin + up_lpm_dfe_n <= up_wdata[1]; + up_cpll_pd <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h05)) begin + up_drp_resetn <= up_wdata[1]; + up_pll_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h08)) begin + up_rx_gt_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h09)) begin + up_rx_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0a)) begin + up_rx_sys_clk_sel <= up_wdata[5:4]; + up_rx_out_clk_sel <= up_wdata[2:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0b)) begin + up_rx_sysref_sel <= up_wdata[1]; + up_rx_sysref <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0c)) begin + up_rx_sync <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0e)) begin + up_rx_user_ready <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin + up_tx_gt_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h19)) begin + up_tx_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1a)) begin + up_tx_sys_clk_sel <= up_wdata[5:4]; + up_tx_out_clk_sel <= up_wdata[2:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1b)) begin + up_tx_sysref_sel <= up_wdata[1]; + up_tx_sysref <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin + up_tx_sync <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin + up_tx_user_ready <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin + up_drp_sel_int <= 1'b1; + up_drp_wr_int <= ~up_wdata[28]; + end else begin + up_drp_sel_int <= 1'b0; + up_drp_wr_int <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin + up_drp_status <= 1'b1; + end else if (up_drp_ready == 1'b1) begin + up_drp_status <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin + up_drp_rwn <= up_wdata[28]; + up_drp_addr_int <= up_wdata[27:16]; + up_drp_wdata_int <= up_wdata[15:0]; + end + if (up_drp_ready_int == 1'b1) begin + up_drp_rdata_hold <= up_drp_rdata_int; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin + up_es_init <= up_wdata[2]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin + up_es_stop <= up_wdata[1]; + up_es_stop_hold <= up_wdata[1]; + end else begin + up_es_stop <= 1'd0; + up_es_stop_hold <= up_es_stop_hold; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin + up_es_start <= up_wdata[0]; + up_es_start_hold <= up_wdata[0]; + end else begin + up_es_start <= 1'd0; + up_es_start_hold <= up_es_start_hold; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin + up_es_prescale <= up_wdata[4:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin + up_es_voffset_range <= up_wdata[25:24]; + up_es_voffset_step <= up_wdata[23:16]; + up_es_voffset_max <= up_wdata[15:8]; + up_es_voffset_min <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin + up_es_hoffset_max <= up_wdata[27:16]; + up_es_hoffset_min <= up_wdata[11:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2c)) begin + up_es_hoffset_step <= up_wdata[11:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2d)) begin + up_es_start_addr <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2e)) begin + up_es_sdata1 <= up_wdata[31:16]; + up_es_sdata0 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin + up_es_sdata3 <= up_wdata[31:16]; + up_es_sdata2 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin + up_es_sdata4 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin + up_es_qdata1 <= up_wdata[31:16]; + up_es_qdata0 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin + up_es_qdata3 <= up_wdata[31:16]; + up_es_qdata2 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin + up_es_qdata4 <= up_wdata[15:0]; + end + if (up_es_dma_err == 1'b1) begin + up_es_dma_err_hold <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin + up_es_dma_err_hold <= up_es_dma_err_hold & ~up_wdata[1]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h04: up_rdata <= {30'd0, up_lpm_dfe_n, up_cpll_pd}; + 8'h05: up_rdata <= {30'd0, up_drp_resetn, up_pll_resetn}; + 8'h08: up_rdata <= {31'd0, up_rx_gt_resetn}; + 8'h09: up_rdata <= {31'd0, up_rx_resetn}; + 8'h0a: up_rdata <= {24'd0, 2'd0, up_rx_sys_clk_sel, 1'd0, up_rx_out_clk_sel}; + 8'h0b: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref}; + 8'h0c: up_rdata <= {31'd0, up_rx_sync}; + 8'h0d: up_rdata <= {15'd0, up_rx_status, + 6'hcf, up_rx_rst_done_m, up_rx_rst_done, + 6'hcf, up_rx_pll_locked_m, up_rx_pll_locked}; + 8'h0e: up_rdata <= {31'd0, up_rx_user_ready}; + 8'h18: up_rdata <= {31'd0, up_tx_gt_resetn}; + 8'h19: up_rdata <= {31'd0, up_tx_resetn}; + 8'h1a: up_rdata <= {24'd0, 2'd0, up_tx_sys_clk_sel, 1'd0, up_tx_out_clk_sel}; + 8'h1b: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref}; + 8'h1c: up_rdata <= {31'd0, up_tx_sync}; + 8'h1d: up_rdata <= {15'd0, up_tx_status, + 6'hcf, up_tx_rst_done_m, up_tx_rst_done, + 6'hcf, up_tx_pll_locked_m, up_tx_pll_locked}; + 8'h1e: up_rdata <= {31'd0, up_tx_user_ready}; + 8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr_int, up_drp_wdata_int}; + 8'h25: up_rdata <= {15'd0, up_drp_status, up_drp_rdata_int}; + 8'h28: up_rdata <= {29'd0, up_es_init, up_es_stop_hold, up_es_start_hold}; + 8'h29: up_rdata <= {27'd0, up_es_prescale}; + 8'h2a: up_rdata <= {6'd0, up_es_voffset_range, up_es_voffset_step, + up_es_voffset_max, up_es_voffset_min}; + 8'h2b: up_rdata <= {4'd0, up_es_hoffset_max, 4'd0, up_es_hoffset_min}; + 8'h2c: up_rdata <= {20'd0, up_es_hoffset_step}; + 8'h2d: up_rdata <= up_es_start_addr; + 8'h2e: up_rdata <= {up_es_sdata1, up_es_sdata0}; + 8'h2f: up_rdata <= {up_es_sdata3, up_es_sdata2}; + 8'h30: up_rdata <= up_es_sdata4; + 8'h31: up_rdata <= {up_es_qdata1, up_es_qdata0}; + 8'h32: up_rdata <= {up_es_qdata3, up_es_qdata2}; + 8'h33: up_rdata <= up_es_qdata4; + 8'h38: up_rdata <= {30'd0, up_es_dma_err_hold, up_es_status}; + 8'h39: up_rdata <= {24'd0, up_drp_rxrate}; + 8'h3a: up_rdata <= GTH_GTX_N; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // resets + + ad_rst i_pll_rst_reg (.preset(up_pll_preset), .clk(up_clk), .rst(pll_rst)); + ad_rst i_rx_gt_rst_reg (.preset(up_rx_gt_preset), .clk(up_clk), .rst(rx_gt_rst)); + ad_rst i_rx_ip_rst_reg (.preset(up_rx_preset), .clk(up_clk), .rst(rx_ip_rst)); + ad_rst i_rx_rst_reg (.preset(up_rx_preset), .clk(rx_clk), .rst(rx_rst)); + ad_rst i_tx_gt_rst_reg (.preset(up_tx_gt_preset), .clk(up_clk), .rst(tx_gt_rst)); + ad_rst i_tx_ip_rst_reg (.preset(up_tx_preset), .clk(up_clk), .rst(tx_ip_rst)); + ad_rst i_tx_rst_reg (.preset(up_tx_preset), .clk(tx_clk), .rst(tx_rst)); + + // reset done & pll locked + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rx_rst_done_m1 <= 'd0; + up_rx_rst_done <= 'd0; + up_rx_rst_done_m_m1 <= 'd0; + up_rx_rst_done_m <= 'd0; + up_rx_pll_locked_m1 <= 'd0; + up_rx_pll_locked <= 'd0; + up_rx_pll_locked_m_m1 <= 'd0; + up_rx_pll_locked_m <= 'd0; + up_rx_status_m1 <= 'd0; + up_rx_status <= 'd0; + up_tx_rst_done_m1 <= 'd0; + up_tx_rst_done <= 'd0; + up_tx_rst_done_m_m1 <= 'd0; + up_tx_rst_done_m <= 'd0; + up_tx_pll_locked_m1 <= 'd0; + up_tx_pll_locked <= 'd0; + up_tx_pll_locked_m_m1 <= 'd0; + up_tx_pll_locked_m <= 'd0; + up_tx_status_m1 <= 'd0; + up_tx_status <= 'd0; + end else begin + up_rx_rst_done_m1 <= rx_rst_done; + up_rx_rst_done <= up_rx_rst_done_m1; + up_rx_rst_done_m_m1 <= rx_rst_done_m; + up_rx_rst_done_m <= up_rx_rst_done_m_m1; + up_rx_pll_locked_m1 <= rx_pll_locked; + up_rx_pll_locked <= up_rx_pll_locked_m1; + up_rx_pll_locked_m_m1 <= rx_pll_locked_m; + up_rx_pll_locked_m <= up_rx_pll_locked_m_m1; + up_rx_status_m1 <= rx_sync; + up_rx_status <= up_rx_status_m1; + up_tx_rst_done_m1 <= tx_rst_done; + up_tx_rst_done <= up_tx_rst_done_m1; + up_tx_rst_done_m_m1 <= tx_rst_done_m; + up_tx_rst_done_m <= up_tx_rst_done_m_m1; + up_tx_pll_locked_m1 <= tx_pll_locked; + up_tx_pll_locked <= up_tx_pll_locked_m1; + up_tx_pll_locked_m_m1 <= tx_pll_locked_m; + up_tx_pll_locked_m <= up_tx_pll_locked_m_m1; + up_tx_status_m1 <= tx_ip_sync; + up_tx_status <= up_tx_status_m1; + end + end + + // drp mux + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_drp_sel <= 'd0; + up_drp_wr <= 'd0; + up_drp_addr <= 'd0; + up_drp_wdata <= 'd0; + up_es_drp_rdata <= 'd0; + up_es_drp_ready <= 'd0; + up_drp_rdata_int <= 'd0; + up_drp_ready_int <= 'd0; + end else begin + if (up_es_status == 1'b1) begin + up_drp_sel <= up_es_drp_sel; + up_drp_wr <= up_es_drp_wr; + up_drp_addr <= up_es_drp_addr; + up_drp_wdata <= up_es_drp_wdata; + up_es_drp_rdata <= up_drp_rdata; + up_es_drp_ready <= up_drp_ready; + up_drp_rdata_int <= 16'd0; + up_drp_ready_int <= 1'd0; + end else begin + up_drp_sel <= up_drp_sel_int; + up_drp_wr <= up_drp_wr_int; + up_drp_addr <= up_drp_addr_int; + up_drp_wdata <= up_drp_wdata_int; + up_es_drp_rdata <= 16'd0; + up_es_drp_ready <= 1'd0; + up_drp_rdata_int <= up_drp_rdata; + up_drp_ready_int <= up_drp_ready; + end + end + end + + // rx sysref & sync + + always @(posedge rx_clk) begin + if (rx_rst_m == 1'b1) begin + rx_sysref_sel_m1 <= 'd0; + rx_sysref_sel <= 'd0; + rx_up_sysref_m1 <= 'd0; + rx_up_sysref <= 'd0; + rx_ip_sysref <= 'd0; + rx_up_sync_m1 <= 'd0; + rx_up_sync <= 'd0; + rx_sync <= 'd0; + end else begin + rx_sysref_sel_m1 <= up_rx_sysref_sel; + rx_sysref_sel <= rx_sysref_sel_m1; + rx_up_sysref_m1 <= up_rx_sysref; + rx_up_sysref <= rx_up_sysref_m1; + if (rx_sysref_sel_m1 == 1'b1) begin + rx_ip_sysref <= rx_sysref; + end else begin + rx_ip_sysref <= rx_up_sysref; + end + rx_up_sync_m1 <= up_rx_sync; + rx_up_sync <= rx_up_sync_m1; + rx_sync <= rx_up_sync & rx_ip_sync; + end + end + + // tx sysref & sync + + always @(posedge tx_clk) begin + if (tx_rst_m == 1'b1) begin + tx_sysref_sel_m1 <= 'd0; + tx_sysref_sel <= 'd0; + tx_up_sysref_m1 <= 'd0; + tx_up_sysref <= 'd0; + tx_ip_sysref <= 'd0; + tx_up_sync_m1 <= 'd0; + tx_up_sync <= 'd0; + tx_ip_sync <= 'd0; + end else begin + tx_sysref_sel_m1 <= up_tx_sysref_sel; + tx_sysref_sel <= tx_sysref_sel_m1; + tx_up_sysref_m1 <= up_tx_sysref; + tx_up_sysref <= tx_up_sysref_m1; + if (tx_sysref_sel_m1 == 1'b1) begin + tx_ip_sysref <= tx_sysref; + end else begin + tx_ip_sysref <= tx_up_sysref; + end + tx_up_sync_m1 <= up_tx_sync; + tx_up_sync <= tx_up_sync_m1; + tx_ip_sync <= tx_up_sync & tx_sync; + end + end + +endmodule + +// *************************************************************************** +// ***************************************************************************