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axi_jesd_gt- per lane split-up

main
Rejeesh Kutty 2015-08-03 08:38:00 -04:00
parent 10a3ce96fe
commit e4b0710923
4 changed files with 3047 additions and 0 deletions
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library/common/ad_gt_channel.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common (
// reset and clocks
qpll_ref_clk_in,
qpll_rst,
qpll_clk,
qpll_ref_clk,
qpll_locked,
// drp interface
up_clk,
up_drp_sel,
up_drp_addr,
up_drp_wr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready);
// parameters
parameter integer GTH_GTX_N = 0;
parameter integer QPLL_ENABLE = 1;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [26:0] QPLL_CFG = 27'h06801C1;
parameter integer QPLL_FBDIV_RATIO = 1'b1;
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000;
// reset and clocks
input qpll_ref_clk_in;
input qpll_rst;
output qpll_clk;
output qpll_ref_clk;
output qpll_locked;
// drp interface
input up_clk;
input up_drp_sel;
input [11:0] up_drp_addr;
input up_drp_wr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
// instantiations
generate
if (QPLL_ENABLE == 0) begin
assign qpll_clk = 1'd0;
assign qpll_ref_clk = 1'd0;
assign qpll_locked = 1'd0;
assign up_drp_rdata = 16'd0;
assign up_drp_ready = 1'd0;
end
if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 0)) begin
GTXE2_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gtxe2_common (
.DRPCLK (up_clk),
.DRPEN (up_drp_sel),
.DRPADDR (up_drp_addr[7:0]),
.DRPWE (up_drp_wr),
.DRPDI (up_drp_wdata),
.DRPDO (up_drp_rdata),
.DRPRDY (up_drp_ready),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (qpll_ref_clk_in),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.QPLLDMONITOR (),
.QPLLOUTCLK (qpll_clk),
.QPLLOUTREFCLK (qpll_ref_clk),
.REFCLKOUTMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (qpll_locked),
.QPLLLOCKDETCLK (up_clk),
.QPLLLOCKEN (1'd1),
.QPLLOUTRESET (1'd0),
.QPLLPD (1'd0),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (qpll_rst),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (1'd1));
end
if ((QPLL_ENABLE == 1) && (GTH_GTX_N == 1)) begin
GTHE3_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION (2),
.SARC_EN (1'b1),
.SARC_SEL (1'b0),
.SDM0_DATA_PIN_SEL (1'b0),
.SDM0_WIDTH_PIN_SEL (1'b0),
.SDM1_DATA_PIN_SEL (1'b0),
.SDM1_WIDTH_PIN_SEL (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000000000000),
.BIAS_CFG3 (16'b0000000001000000),
.BIAS_CFG4 (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000100),
.QPLL0_CFG0 (16'b0011000000011100),
.QPLL0_CFG1 (16'b0000000000011000),
.QPLL0_CFG1_G3 (16'b0000000000011000),
.QPLL0_CFG2 (16'b0000000001001000),
.QPLL0_CFG2_G3 (16'b0000000001001000),
.QPLL0_CFG3 (16'b0000000100100000),
.QPLL0_CFG4 (16'b0000000000001001),
.QPLL0_INIT_CFG0 (16'b0000000000000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_SDM_CFG0 (16'b0000000000000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1_CFG0 (16'b0011000000011100),
.QPLL1_CFG1 (16'b0000000000011000),
.QPLL1_CFG1_G3 (16'b0000000000011000),
.QPLL1_CFG2 (16'b0000000001000000),
.QPLL1_CFG2_G3 (16'b0000000001000000),
.QPLL1_CFG3 (16'b0000000100100000),
.QPLL1_CFG4 (16'b0000000000001001),
.QPLL1_INIT_CFG0 (16'b0000000000000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_SDM_CFG0 (16'b0000000000000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.SDM0DATA1_0 (16'b0000000000000000),
.SDM0INITSEED0_0 (16'b0000000000000000),
.SDM1DATA1_0 (16'b0000000000000000),
.SDM1INITSEED0_0 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL1_INIT_CFG1 (8'b00000000),
.SDM0DATA1_1 (9'b000000000),
.SDM0INITSEED0_1 (9'b000000000),
.SDM1DATA1_1 (9'b000000000),
.SDM1INITSEED0_1 (9'b000000000),
.BIAS_CFG_RSVD (10'b0000000000),
.QPLL0_CP (10'b0000011111),
.QPLL0_CP_G3 (10'b1111111111),
.QPLL0_LPF (10'b1111111111),
.QPLL0_LPF_G3 (10'b0000010101),
.QPLL1_CP (10'b0000011111),
.QPLL1_CP_G3 (10'b1111111111),
.QPLL1_LPF (10'b1111111111),
.QPLL1_LPF_G3 (10'b0000010101),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (80),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gthe3_common (
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'd1),
.DRPADDR (up_drp_addr[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata),
.DRPEN (up_drp_sel),
.DRPWE (up_drp_wr),
.GTGREFCLK0 (1'd0),
.GTGREFCLK1 (1'd0),
.GTNORTHREFCLK00 (1'd0),
.GTNORTHREFCLK01 (1'd0),
.GTNORTHREFCLK10 (1'd0),
.GTNORTHREFCLK11 (1'd0),
.GTREFCLK00 (qpll_ref_clk_in),
.GTREFCLK01 (1'd0),
.GTREFCLK10 (1'd0),
.GTREFCLK11 (1'd0),
.GTSOUTHREFCLK00 (1'd0),
.GTSOUTHREFCLK01 (1'd0),
.GTSOUTHREFCLK10 (1'd0),
.GTSOUTHREFCLK11 (1'd0),
.PMARSVD0 (8'd0),
.PMARSVD1 (8'd0),
.QPLLRSVD1 (8'd0),
.QPLLRSVD2 (5'd0),
.QPLLRSVD3 (5'd0),
.QPLLRSVD4 (8'd0),
.QPLL0CLKRSVD0 (1'd0),
.QPLL0CLKRSVD1 (1'd0),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'd1),
.QPLL0PD (1'd0),
.QPLL0REFCLKSEL (3'b001),
.QPLL0RESET (qpll_rst),
.QPLL1CLKRSVD0 (1'd0),
.QPLL1CLKRSVD1 (1'd0),
.QPLL1LOCKDETCLK (1'd0),
.QPLL1LOCKEN (1'd0),
.QPLL1PD (1'd1),
.QPLL1REFCLKSEL (3'b001),
.QPLL1RESET (1'd1),
.RCALENB (1'd1),
.DRPDO (up_drp_rdata),
.DRPRDY (up_drp_ready),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLL0FBCLKLOST (),
.QPLL0LOCK (qpll_locked),
.QPLL0OUTCLK (qpll_clk),
.QPLL0OUTREFCLK (qpll_ref_clk),
.QPLL0REFCLKLOST (),
.QPLL1FBCLKLOST (),
.QPLL1LOCK (),
.QPLL1OUTCLK (),
.QPLL1OUTREFCLK (),
.QPLL1REFCLKLOST (),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0_SEL (),
.RXRECCLK1_SEL ());
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_gt_es_axi (
// es interface
up_rstn,
up_clk,
up_es_dma_req_0,
up_es_dma_addr_0,
up_es_dma_data_0,
up_es_dma_ack_0,
up_es_dma_err_0,
up_es_dma_req_1,
up_es_dma_addr_1,
up_es_dma_data_1,
up_es_dma_ack_1,
up_es_dma_err_1,
up_es_dma_req_2,
up_es_dma_addr_2,
up_es_dma_data_2,
up_es_dma_ack_2,
up_es_dma_err_2,
up_es_dma_req_3,
up_es_dma_addr_3,
up_es_dma_data_3,
up_es_dma_ack_3,
up_es_dma_err_3,
up_es_dma_req_4,
up_es_dma_addr_4,
up_es_dma_data_4,
up_es_dma_ack_4,
up_es_dma_err_4,
up_es_dma_req_5,
up_es_dma_addr_5,
up_es_dma_data_5,
up_es_dma_ack_5,
up_es_dma_err_5,
up_es_dma_req_6,
up_es_dma_addr_6,
up_es_dma_data_6,
up_es_dma_ack_6,
up_es_dma_err_6,
up_es_dma_req_7,
up_es_dma_addr_7,
up_es_dma_data_7,
up_es_dma_ack_7,
up_es_dma_err_7,
// axi4 interface
axi_awvalid,
axi_awaddr,
axi_awprot,
axi_awready,
axi_wvalid,
axi_wdata,
axi_wstrb,
axi_wready,
axi_bvalid,
axi_bresp,
axi_bready,
axi_arvalid,
axi_araddr,
axi_arprot,
axi_arready,
axi_rvalid,
axi_rresp,
axi_rdata,
axi_rready);
// state machine (fair RR?)
localparam [ 3:0] AXI_FSM_SCAN_0 = 4'h0;
localparam [ 3:0] AXI_FSM_SCAN_1 = 4'h1;
localparam [ 3:0] AXI_FSM_SCAN_2 = 4'h2;
localparam [ 3:0] AXI_FSM_SCAN_3 = 4'h3;
localparam [ 3:0] AXI_FSM_SCAN_4 = 4'h4;
localparam [ 3:0] AXI_FSM_SCAN_5 = 4'h5;
localparam [ 3:0] AXI_FSM_SCAN_6 = 4'h6;
localparam [ 3:0] AXI_FSM_SCAN_7 = 4'h7;
localparam [ 3:0] AXI_FSM_WRITE = 4'h8;
localparam [ 3:0] AXI_FSM_WAIT = 4'h9;
localparam [ 3:0] AXI_FSM_ACK = 4'ha;
// es interface
input up_rstn;
input up_clk;
input up_es_dma_req_0;
input [31:0] up_es_dma_addr_0;
input [31:0] up_es_dma_data_0;
output up_es_dma_ack_0;
output up_es_dma_err_0;
input up_es_dma_req_1;
input [31:0] up_es_dma_addr_1;
input [31:0] up_es_dma_data_1;
output up_es_dma_ack_1;
output up_es_dma_err_1;
input up_es_dma_req_2;
input [31:0] up_es_dma_addr_2;
input [31:0] up_es_dma_data_2;
output up_es_dma_ack_2;
output up_es_dma_err_2;
input up_es_dma_req_3;
input [31:0] up_es_dma_addr_3;
input [31:0] up_es_dma_data_3;
output up_es_dma_ack_3;
output up_es_dma_err_3;
input up_es_dma_req_4;
input [31:0] up_es_dma_addr_4;
input [31:0] up_es_dma_data_4;
output up_es_dma_ack_4;
output up_es_dma_err_4;
input up_es_dma_req_5;
input [31:0] up_es_dma_addr_5;
input [31:0] up_es_dma_data_5;
output up_es_dma_ack_5;
output up_es_dma_err_5;
input up_es_dma_req_6;
input [31:0] up_es_dma_addr_6;
input [31:0] up_es_dma_data_6;
output up_es_dma_ack_6;
output up_es_dma_err_6;
input up_es_dma_req_7;
input [31:0] up_es_dma_addr_7;
input [31:0] up_es_dma_data_7;
output up_es_dma_ack_7;
output up_es_dma_err_7;
// axi4 interface
output axi_awvalid;
output [31:0] axi_awaddr;
output [ 2:0] axi_awprot;
input axi_awready;
output axi_wvalid;
output [31:0] axi_wdata;
output [ 3:0] axi_wstrb;
input axi_wready;
input axi_bvalid;
input [ 1:0] axi_bresp;
output axi_bready;
output axi_arvalid;
output [31:0] axi_araddr;
output [ 2:0] axi_arprot;
input axi_arready;
input axi_rvalid;
input [31:0] axi_rdata;
input [ 1:0] axi_rresp;
output axi_rready;
// internal registers
reg up_es_dma_ack_0 = 'd0;
reg up_es_dma_err_0 = 'd0;
reg up_es_dma_ack_1 = 'd0;
reg up_es_dma_err_1 = 'd0;
reg up_es_dma_ack_2 = 'd0;
reg up_es_dma_err_2 = 'd0;
reg up_es_dma_ack_3 = 'd0;
reg up_es_dma_err_3 = 'd0;
reg up_es_dma_ack_4 = 'd0;
reg up_es_dma_err_4 = 'd0;
reg up_es_dma_ack_5 = 'd0;
reg up_es_dma_err_5 = 'd0;
reg up_es_dma_ack_6 = 'd0;
reg up_es_dma_err_6 = 'd0;
reg up_es_dma_ack_7 = 'd0;
reg up_es_dma_err_7 = 'd0;
reg axi_awvalid = 'd0;
reg [31:0] axi_awaddr = 'd0;
reg axi_wvalid = 'd0;
reg [31:0] axi_wdata = 'd0;
reg axi_error = 'd0;
reg [ 2:0] axi_sel = 'd0;
reg [ 3:0] axi_fsm = 'd0;
// axi write interface
assign axi_awprot = 3'd0;
assign axi_wstrb = 4'hf;
assign axi_bready = 1'd1;
assign axi_arvalid = 1'd0;
assign axi_araddr = 32'd0;
assign axi_arprot = 3'd0;
assign axi_rready = 1'd1;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_es_dma_ack_0 <= 1'b0;
up_es_dma_err_0 <= 1'b0;
up_es_dma_ack_1 <= 1'b0;
up_es_dma_err_1 <= 1'b0;
up_es_dma_ack_2 <= 1'b0;
up_es_dma_err_2 <= 1'b0;
up_es_dma_ack_3 <= 1'b0;
up_es_dma_err_3 <= 1'b0;
up_es_dma_ack_4 <= 1'b0;
up_es_dma_err_4 <= 1'b0;
up_es_dma_ack_5 <= 1'b0;
up_es_dma_err_5 <= 1'b0;
up_es_dma_ack_6 <= 1'b0;
up_es_dma_err_6 <= 1'b0;
up_es_dma_ack_7 <= 1'b0;
up_es_dma_err_7 <= 1'b0;
end else begin
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd0)) begin
up_es_dma_ack_0 <= 1'b1;
up_es_dma_err_0 <= axi_error;
end else begin
up_es_dma_ack_0 <= 1'b0;
up_es_dma_err_0 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd1)) begin
up_es_dma_ack_1 <= 1'b1;
up_es_dma_err_1 <= axi_error;
end else begin
up_es_dma_ack_1 <= 1'b0;
up_es_dma_err_1 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd2)) begin
up_es_dma_ack_2 <= 1'b1;
up_es_dma_err_2 <= axi_error;
end else begin
up_es_dma_ack_2 <= 1'b0;
up_es_dma_err_2 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd3)) begin
up_es_dma_ack_3 <= 1'b1;
up_es_dma_err_3 <= axi_error;
end else begin
up_es_dma_ack_3 <= 1'b0;
up_es_dma_err_3 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd4)) begin
up_es_dma_ack_4 <= 1'b1;
up_es_dma_err_4 <= axi_error;
end else begin
up_es_dma_ack_4 <= 1'b0;
up_es_dma_err_4 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd5)) begin
up_es_dma_ack_5 <= 1'b1;
up_es_dma_err_5 <= axi_error;
end else begin
up_es_dma_ack_5 <= 1'b0;
up_es_dma_err_5 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd6)) begin
up_es_dma_ack_6 <= 1'b1;
up_es_dma_err_6 <= axi_error;
end else begin
up_es_dma_ack_6 <= 1'b0;
up_es_dma_err_6 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd7)) begin
up_es_dma_ack_7 <= 1'b1;
up_es_dma_err_7 <= axi_error;
end else begin
up_es_dma_ack_7 <= 1'b0;
up_es_dma_err_7 <= 1'b0;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
axi_awvalid <= 'b0;
axi_awaddr <= 'd0;
axi_wvalid <= 'b0;
axi_wdata <= 'd0;
axi_error <= 'd0;
end else begin
if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awvalid <= 1'b0;
axi_awaddr <= 32'd0;
end else if (axi_fsm == AXI_FSM_WRITE) begin
axi_awvalid <= 1'b1;
case (axi_sel)
3'b000: axi_awaddr <= up_es_dma_addr_0;
3'b001: axi_awaddr <= up_es_dma_addr_1;
3'b010: axi_awaddr <= up_es_dma_addr_2;
3'b011: axi_awaddr <= up_es_dma_addr_3;
3'b100: axi_awaddr <= up_es_dma_addr_4;
3'b101: axi_awaddr <= up_es_dma_addr_5;
3'b110: axi_awaddr <= up_es_dma_addr_6;
default: axi_awaddr <= up_es_dma_addr_7;
endcase
end
if ((axi_wvalid == 1'b1) && (axi_wready == 1'b1)) begin
axi_wvalid <= 1'b0;
axi_wdata <= 32'd0;
end else if (axi_fsm == AXI_FSM_WRITE) begin
axi_wvalid <= 1'b1;
case (axi_sel)
3'b000: axi_wdata <= up_es_dma_data_0;
3'b001: axi_wdata <= up_es_dma_data_1;
3'b010: axi_wdata <= up_es_dma_data_2;
3'b011: axi_wdata <= up_es_dma_data_3;
3'b100: axi_wdata <= up_es_dma_data_4;
3'b101: axi_wdata <= up_es_dma_data_5;
3'b110: axi_wdata <= up_es_dma_data_6;
default: axi_wdata <= up_es_dma_data_7;
endcase
end
if (axi_bvalid == 1'b1) begin
axi_error <= axi_bresp[1] | axi_bresp[0];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
axi_sel <= 3'd0;
axi_fsm <= AXI_FSM_SCAN_0;
end else begin
case (axi_fsm)
AXI_FSM_SCAN_0: begin
axi_sel <= 3'd0;
if (up_es_dma_req_0 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_1;
end
end
AXI_FSM_SCAN_1: begin
axi_sel <= 3'd1;
if (up_es_dma_req_1 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_2;
end
end
AXI_FSM_SCAN_2: begin
axi_sel <= 3'd2;
if (up_es_dma_req_2 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_3;
end
end
AXI_FSM_SCAN_3: begin
axi_sel <= 3'd3;
if (up_es_dma_req_3 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_4;
end
end
AXI_FSM_SCAN_4: begin
axi_sel <= 3'd4;
if (up_es_dma_req_4 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_5;
end
end
AXI_FSM_SCAN_5: begin
axi_sel <= 3'd5;
if (up_es_dma_req_5 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_6;
end
end
AXI_FSM_SCAN_6: begin
axi_sel <= 3'd6;
if (up_es_dma_req_6 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_7;
end
end
AXI_FSM_SCAN_7: begin
axi_sel <= 3'd7;
if (up_es_dma_req_7 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_0;
end
end
AXI_FSM_WRITE: begin
axi_sel <= axi_sel;
axi_fsm <= AXI_FSM_WAIT;
end
AXI_FSM_WAIT: begin
axi_sel <= axi_sel;
if (axi_bvalid == 1'b1) begin
axi_fsm <= AXI_FSM_ACK;
end else begin
axi_fsm <= AXI_FSM_WAIT;
end
end
AXI_FSM_ACK: begin
axi_sel <= axi_sel;
case (axi_sel)
3'b000: axi_fsm <= AXI_FSM_SCAN_1;
3'b001: axi_fsm <= AXI_FSM_SCAN_2;
3'b010: axi_fsm <= AXI_FSM_SCAN_3;
3'b011: axi_fsm <= AXI_FSM_SCAN_4;
3'b100: axi_fsm <= AXI_FSM_SCAN_5;
3'b101: axi_fsm <= AXI_FSM_SCAN_6;
3'b110: axi_fsm <= AXI_FSM_SCAN_7;
default: axi_fsm <= AXI_FSM_SCAN_0;
endcase
end
default: begin
axi_fsm <= AXI_FSM_SCAN_0;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_gt_channel (
// gt interface
pll_rst,
lpm_dfe_n,
cpll_pd,
// receive interface
rx_sys_clk_sel,
rx_out_clk_sel,
rx_clk,
rx_gt_rst,
rx_rst,
rx_rst_m,
rx_ip_rst,
rx_sysref,
rx_ip_sysref,
rx_ip_sync,
rx_sync,
rx_rst_done,
rx_rst_done_m,
rx_pll_locked,
rx_pll_locked_m,
rx_user_ready,
rx_ip_rst_done,
// transmit interface
tx_sys_clk_sel,
tx_out_clk_sel,
tx_clk,
tx_gt_rst,
tx_rst,
tx_rst_m,
tx_ip_rst,
tx_sysref,
tx_ip_sysref,
tx_sync,
tx_ip_sync,
tx_rst_done,
tx_rst_done_m,
tx_pll_locked,
tx_pll_locked_m,
tx_user_ready,
tx_ip_rst_done,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_rxrate,
// es interface
up_es_drp_sel,
up_es_drp_wr,
up_es_drp_addr,
up_es_drp_wdata,
up_es_drp_rdata,
up_es_drp_ready,
up_es_start,
up_es_stop,
up_es_init,
up_es_prescale,
up_es_voffset_range,
up_es_voffset_step,
up_es_voffset_max,
up_es_voffset_min,
up_es_hoffset_max,
up_es_hoffset_min,
up_es_hoffset_step,
up_es_start_addr,
up_es_sdata0,
up_es_sdata1,
up_es_sdata2,
up_es_sdata3,
up_es_sdata4,
up_es_qdata0,
up_es_qdata1,
up_es_qdata2,
up_es_qdata3,
up_es_qdata4,
up_es_dma_err,
up_es_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter integer ID = 0;
parameter integer GTH_GTX_N = 0;
// gt interface
output pll_rst;
output lpm_dfe_n;
output cpll_pd;
// receive interface
output [ 1:0] rx_sys_clk_sel;
output [ 2:0] rx_out_clk_sel;
input rx_clk;
output rx_gt_rst;
output rx_rst;
input rx_rst_m;
output rx_ip_rst;
input rx_sysref;
output rx_ip_sysref;
input rx_ip_sync;
output rx_sync;
input rx_rst_done;
input rx_rst_done_m;
input rx_pll_locked;
input rx_pll_locked_m;
output rx_user_ready;
output rx_ip_rst_done;
// transmit interface
output [ 1:0] tx_sys_clk_sel;
output [ 2:0] tx_out_clk_sel;
input tx_clk;
output tx_gt_rst;
output tx_rst;
input tx_rst_m;
output tx_ip_rst;
input tx_sysref;
output tx_ip_sysref;
input tx_sync;
output tx_ip_sync;
input tx_rst_done;
input tx_rst_done_m;
input tx_pll_locked;
input tx_pll_locked_m;
output tx_user_ready;
output tx_ip_rst_done;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input [ 7:0] up_drp_rxrate;
// es interface
input up_es_drp_sel;
input up_es_drp_wr;
input [11:0] up_es_drp_addr;
input [15:0] up_es_drp_wdata;
output [15:0] up_es_drp_rdata;
output up_es_drp_ready;
output up_es_start;
output up_es_stop;
output up_es_init;
output [ 4:0] up_es_prescale;
output [ 1:0] up_es_voffset_range;
output [ 7:0] up_es_voffset_step;
output [ 7:0] up_es_voffset_max;
output [ 7:0] up_es_voffset_min;
output [11:0] up_es_hoffset_max;
output [11:0] up_es_hoffset_min;
output [11:0] up_es_hoffset_step;
output [31:0] up_es_start_addr;
output [15:0] up_es_sdata0;
output [15:0] up_es_sdata1;
output [15:0] up_es_sdata2;
output [15:0] up_es_sdata3;
output [15:0] up_es_sdata4;
output [15:0] up_es_qdata0;
output [15:0] up_es_qdata1;
output [15:0] up_es_qdata2;
output [15:0] up_es_qdata3;
output [15:0] up_es_qdata4;
input up_es_dma_err;
input up_es_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_pll_preset = 'd1;
reg up_rx_gt_preset = 'd1;
reg up_rx_preset = 'd1;
reg up_tx_gt_preset = 'd1;
reg up_tx_preset = 'd1;
reg up_wack = 'd0;
reg up_lpm_dfe_n = 'd0;
reg up_cpll_pd = 'd0;
reg up_drp_resetn = 'd0;
reg up_pll_resetn = 'd0;
reg up_rx_gt_resetn = 'd0;
reg up_rx_resetn = 'd0;
reg [ 1:0] up_rx_sys_clk_sel = 'd0;
reg [ 2:0] up_rx_out_clk_sel = 'd0;
reg up_rx_sysref_sel = 'd0;
reg up_rx_sysref = 'd0;
reg up_rx_sync = 'd0;
reg up_rx_user_ready = 'd0;
reg up_tx_gt_resetn = 'd0;
reg up_tx_resetn = 'd0;
reg [ 1:0] up_tx_sys_clk_sel = 'd0;
reg [ 2:0] up_tx_out_clk_sel = 'd0;
reg up_tx_sysref_sel = 'd0;
reg up_tx_sysref = 'd0;
reg up_tx_sync = 'd0;
reg up_tx_user_ready = 'd0;
reg up_drp_sel_int = 'd0;
reg up_drp_wr_int = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg [15:0] up_drp_wdata_int = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_es_init = 'd0;
reg up_es_stop = 'd0;
reg up_es_stop_hold = 'd0;
reg up_es_start = 'd0;
reg up_es_start_hold = 'd0;
reg [ 4:0] up_es_prescale = 'd0;
reg [ 1:0] up_es_voffset_range = 'd0;
reg [ 7:0] up_es_voffset_step = 'd0;
reg [ 7:0] up_es_voffset_max = 'd0;
reg [ 7:0] up_es_voffset_min = 'd0;
reg [11:0] up_es_hoffset_max = 'd0;
reg [11:0] up_es_hoffset_min = 'd0;
reg [11:0] up_es_hoffset_step = 'd0;
reg [31:0] up_es_start_addr = 'd0;
reg [15:0] up_es_sdata1 = 'd0;
reg [15:0] up_es_sdata0 = 'd0;
reg [15:0] up_es_sdata3 = 'd0;
reg [15:0] up_es_sdata2 = 'd0;
reg [15:0] up_es_sdata4 = 'd0;
reg [15:0] up_es_qdata1 = 'd0;
reg [15:0] up_es_qdata0 = 'd0;
reg [15:0] up_es_qdata3 = 'd0;
reg [15:0] up_es_qdata2 = 'd0;
reg [15:0] up_es_qdata4 = 'd0;
reg up_es_dma_err_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rx_rst_done_m1 = 'd0;
reg up_rx_rst_done = 'd0;
reg up_rx_rst_done_m_m1 = 'd0;
reg up_rx_rst_done_m = 'd0;
reg up_rx_pll_locked_m1 = 'd0;
reg up_rx_pll_locked = 'd0;
reg up_rx_pll_locked_m_m1 = 'd0;
reg up_rx_pll_locked_m = 'd0;
reg up_rx_status_m1 = 'd0;
reg up_rx_status = 'd0;
reg up_tx_rst_done_m1 = 'd0;
reg up_tx_rst_done = 'd0;
reg up_tx_rst_done_m_m1 = 'd0;
reg up_tx_rst_done_m = 'd0;
reg up_tx_pll_locked_m1 = 'd0;
reg up_tx_pll_locked = 'd0;
reg up_tx_pll_locked_m_m1 = 'd0;
reg up_tx_pll_locked_m = 'd0;
reg up_tx_status_m1 = 'd0;
reg up_tx_status = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_es_drp_rdata = 'd0;
reg up_es_drp_ready = 'd0;
reg [15:0] up_drp_rdata_int = 'd0;
reg up_drp_ready_int = 'd0;
reg rx_sysref_sel_m1 = 'd0;
reg rx_sysref_sel = 'd0;
reg rx_up_sysref_m1 = 'd0;
reg rx_up_sysref = 'd0;
reg rx_ip_sysref = 'd0;
reg rx_up_sync_m1 = 'd0;
reg rx_up_sync = 'd0;
reg rx_sync = 'd0;
reg tx_sysref_sel_m1 = 'd0;
reg tx_sysref_sel = 'd0;
reg tx_up_sysref_m1 = 'd0;
reg tx_up_sysref = 'd0;
reg tx_ip_sysref = 'd0;
reg tx_up_sync_m1 = 'd0;
reg tx_up_sync = 'd0;
reg tx_ip_sync = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == ID) ? up_rreq : 1'b0;
// user ready & ip reset done
assign lpm_dfe_n = up_lpm_dfe_n;
assign cpll_pd = up_cpll_pd;
assign rx_sys_clk_sel = up_rx_sys_clk_sel;
assign rx_out_clk_sel = up_rx_out_clk_sel;
assign rx_user_ready = up_rx_user_ready;
assign rx_ip_rst_done = up_rx_rst_done_m;
assign tx_sys_clk_sel = up_tx_sys_clk_sel;
assign tx_out_clk_sel = up_tx_out_clk_sel;
assign tx_user_ready = up_tx_user_ready;
assign tx_ip_rst_done = up_tx_rst_done_m;
// resets
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_pll_preset <= 1'b1;
up_rx_gt_preset <= 1'b1;
up_tx_gt_preset <= 1'b1;
up_rx_preset <= 1'b1;
up_tx_preset <= 1'b1;
end else begin
up_pll_preset <= ~up_pll_resetn;
up_rx_gt_preset <= ~(up_pll_resetn &
up_rx_pll_locked_m & up_rx_gt_resetn);
up_rx_preset <= ~(up_pll_resetn & up_rx_pll_locked_m &
up_rx_rst_done_m & up_rx_gt_resetn & up_rx_resetn);
up_tx_gt_preset <= ~(up_pll_resetn &
up_tx_pll_locked_m & up_tx_gt_resetn);
up_tx_preset <= ~(up_pll_resetn & up_tx_pll_locked_m &
up_tx_rst_done_m & up_tx_gt_resetn & up_tx_resetn);
end
end
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_lpm_dfe_n <= 'd0;
up_cpll_pd <= 'd1;
up_drp_resetn <= 'd0;
up_pll_resetn <= 'd0;
up_rx_gt_resetn <= 'd0;
up_rx_resetn <= 'd0;
up_rx_sys_clk_sel <= 2'b11;
up_rx_out_clk_sel <= 3'b010;
up_rx_sysref_sel <= 'd0;
up_rx_sysref <= 'd0;
up_rx_sync <= 'd0;
up_rx_user_ready <= 'd0;
up_tx_gt_resetn <= 'd0;
up_tx_resetn <= 'd0;
up_tx_sys_clk_sel <= 2'b11;
up_tx_out_clk_sel <= 3'b010;
up_tx_sysref_sel <= 'd0;
up_tx_sysref <= 'd0;
up_tx_sync <= 'd0;
up_tx_user_ready <= 'd0;
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
up_es_init <= 'd0;
up_es_stop <= 'd0;
up_es_stop_hold <= 'd0;
up_es_start <= 'd0;
up_es_start_hold <= 'd0;
up_es_prescale <= 'd0;
up_es_voffset_range <= 'd0;
up_es_voffset_step <= 'd0;
up_es_voffset_max <= 'd0;
up_es_voffset_min <= 'd0;
up_es_hoffset_max <= 'd0;
up_es_hoffset_min <= 'd0;
up_es_hoffset_step <= 'd0;
up_es_start_addr <= 'd0;
up_es_sdata1 <= 'd0;
up_es_sdata0 <= 'd0;
up_es_sdata3 <= 'd0;
up_es_sdata2 <= 'd0;
up_es_sdata4 <= 'd0;
up_es_qdata1 <= 'd0;
up_es_qdata0 <= 'd0;
up_es_qdata3 <= 'd0;
up_es_qdata2 <= 'd0;
up_es_qdata4 <= 'd0;
up_es_dma_err_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_lpm_dfe_n <= up_wdata[1];
up_cpll_pd <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h05)) begin
up_drp_resetn <= up_wdata[1];
up_pll_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h08)) begin
up_rx_gt_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h09)) begin
up_rx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0a)) begin
up_rx_sys_clk_sel <= up_wdata[5:4];
up_rx_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0b)) begin
up_rx_sysref_sel <= up_wdata[1];
up_rx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0c)) begin
up_rx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0e)) begin
up_rx_user_ready <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
up_tx_gt_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h19)) begin
up_tx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1a)) begin
up_tx_sys_clk_sel <= up_wdata[5:4];
up_tx_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1b)) begin
up_tx_sysref_sel <= up_wdata[1];
up_tx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_tx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
up_tx_user_ready <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_sel_int <= 1'b1;
up_drp_wr_int <= ~up_wdata[28];
end else begin
up_drp_sel_int <= 1'b0;
up_drp_wr_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr_int <= up_wdata[27:16];
up_drp_wdata_int <= up_wdata[15:0];
end
if (up_drp_ready_int == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata_int;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_init <= up_wdata[2];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_stop <= up_wdata[1];
up_es_stop_hold <= up_wdata[1];
end else begin
up_es_stop <= 1'd0;
up_es_stop_hold <= up_es_stop_hold;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_start <= up_wdata[0];
up_es_start_hold <= up_wdata[0];
end else begin
up_es_start <= 1'd0;
up_es_start_hold <= up_es_start_hold;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_es_prescale <= up_wdata[4:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
up_es_voffset_range <= up_wdata[25:24];
up_es_voffset_step <= up_wdata[23:16];
up_es_voffset_max <= up_wdata[15:8];
up_es_voffset_min <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
up_es_hoffset_max <= up_wdata[27:16];
up_es_hoffset_min <= up_wdata[11:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2c)) begin
up_es_hoffset_step <= up_wdata[11:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2d)) begin
up_es_start_addr <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2e)) begin
up_es_sdata1 <= up_wdata[31:16];
up_es_sdata0 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_es_sdata3 <= up_wdata[31:16];
up_es_sdata2 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
up_es_sdata4 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
up_es_qdata1 <= up_wdata[31:16];
up_es_qdata0 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_es_qdata3 <= up_wdata[31:16];
up_es_qdata2 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_es_qdata4 <= up_wdata[15:0];
end
if (up_es_dma_err == 1'b1) begin
up_es_dma_err_hold <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_es_dma_err_hold <= up_es_dma_err_hold & ~up_wdata[1];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h04: up_rdata <= {30'd0, up_lpm_dfe_n, up_cpll_pd};
8'h05: up_rdata <= {30'd0, up_drp_resetn, up_pll_resetn};
8'h08: up_rdata <= {31'd0, up_rx_gt_resetn};
8'h09: up_rdata <= {31'd0, up_rx_resetn};
8'h0a: up_rdata <= {24'd0, 2'd0, up_rx_sys_clk_sel, 1'd0, up_rx_out_clk_sel};
8'h0b: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
8'h0c: up_rdata <= {31'd0, up_rx_sync};
8'h0d: up_rdata <= {15'd0, up_rx_status,
6'hcf, up_rx_rst_done_m, up_rx_rst_done,
6'hcf, up_rx_pll_locked_m, up_rx_pll_locked};
8'h0e: up_rdata <= {31'd0, up_rx_user_ready};
8'h18: up_rdata <= {31'd0, up_tx_gt_resetn};
8'h19: up_rdata <= {31'd0, up_tx_resetn};
8'h1a: up_rdata <= {24'd0, 2'd0, up_tx_sys_clk_sel, 1'd0, up_tx_out_clk_sel};
8'h1b: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h1c: up_rdata <= {31'd0, up_tx_sync};
8'h1d: up_rdata <= {15'd0, up_tx_status,
6'hcf, up_tx_rst_done_m, up_tx_rst_done,
6'hcf, up_tx_pll_locked_m, up_tx_pll_locked};
8'h1e: up_rdata <= {31'd0, up_tx_user_ready};
8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr_int, up_drp_wdata_int};
8'h25: up_rdata <= {15'd0, up_drp_status, up_drp_rdata_int};
8'h28: up_rdata <= {29'd0, up_es_init, up_es_stop_hold, up_es_start_hold};
8'h29: up_rdata <= {27'd0, up_es_prescale};
8'h2a: up_rdata <= {6'd0, up_es_voffset_range, up_es_voffset_step,
up_es_voffset_max, up_es_voffset_min};
8'h2b: up_rdata <= {4'd0, up_es_hoffset_max, 4'd0, up_es_hoffset_min};
8'h2c: up_rdata <= {20'd0, up_es_hoffset_step};
8'h2d: up_rdata <= up_es_start_addr;
8'h2e: up_rdata <= {up_es_sdata1, up_es_sdata0};
8'h2f: up_rdata <= {up_es_sdata3, up_es_sdata2};
8'h30: up_rdata <= up_es_sdata4;
8'h31: up_rdata <= {up_es_qdata1, up_es_qdata0};
8'h32: up_rdata <= {up_es_qdata3, up_es_qdata2};
8'h33: up_rdata <= up_es_qdata4;
8'h38: up_rdata <= {30'd0, up_es_dma_err_hold, up_es_status};
8'h39: up_rdata <= {24'd0, up_drp_rxrate};
8'h3a: up_rdata <= GTH_GTX_N;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_pll_rst_reg (.preset(up_pll_preset), .clk(up_clk), .rst(pll_rst));
ad_rst i_rx_gt_rst_reg (.preset(up_rx_gt_preset), .clk(up_clk), .rst(rx_gt_rst));
ad_rst i_rx_ip_rst_reg (.preset(up_rx_preset), .clk(up_clk), .rst(rx_ip_rst));
ad_rst i_rx_rst_reg (.preset(up_rx_preset), .clk(rx_clk), .rst(rx_rst));
ad_rst i_tx_gt_rst_reg (.preset(up_tx_gt_preset), .clk(up_clk), .rst(tx_gt_rst));
ad_rst i_tx_ip_rst_reg (.preset(up_tx_preset), .clk(up_clk), .rst(tx_ip_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_preset), .clk(tx_clk), .rst(tx_rst));
// reset done & pll locked
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rx_rst_done_m1 <= 'd0;
up_rx_rst_done <= 'd0;
up_rx_rst_done_m_m1 <= 'd0;
up_rx_rst_done_m <= 'd0;
up_rx_pll_locked_m1 <= 'd0;
up_rx_pll_locked <= 'd0;
up_rx_pll_locked_m_m1 <= 'd0;
up_rx_pll_locked_m <= 'd0;
up_rx_status_m1 <= 'd0;
up_rx_status <= 'd0;
up_tx_rst_done_m1 <= 'd0;
up_tx_rst_done <= 'd0;
up_tx_rst_done_m_m1 <= 'd0;
up_tx_rst_done_m <= 'd0;
up_tx_pll_locked_m1 <= 'd0;
up_tx_pll_locked <= 'd0;
up_tx_pll_locked_m_m1 <= 'd0;
up_tx_pll_locked_m <= 'd0;
up_tx_status_m1 <= 'd0;
up_tx_status <= 'd0;
end else begin
up_rx_rst_done_m1 <= rx_rst_done;
up_rx_rst_done <= up_rx_rst_done_m1;
up_rx_rst_done_m_m1 <= rx_rst_done_m;
up_rx_rst_done_m <= up_rx_rst_done_m_m1;
up_rx_pll_locked_m1 <= rx_pll_locked;
up_rx_pll_locked <= up_rx_pll_locked_m1;
up_rx_pll_locked_m_m1 <= rx_pll_locked_m;
up_rx_pll_locked_m <= up_rx_pll_locked_m_m1;
up_rx_status_m1 <= rx_sync;
up_rx_status <= up_rx_status_m1;
up_tx_rst_done_m1 <= tx_rst_done;
up_tx_rst_done <= up_tx_rst_done_m1;
up_tx_rst_done_m_m1 <= tx_rst_done_m;
up_tx_rst_done_m <= up_tx_rst_done_m_m1;
up_tx_pll_locked_m1 <= tx_pll_locked;
up_tx_pll_locked <= up_tx_pll_locked_m1;
up_tx_pll_locked_m_m1 <= tx_pll_locked_m;
up_tx_pll_locked_m <= up_tx_pll_locked_m_m1;
up_tx_status_m1 <= tx_ip_sync;
up_tx_status <= up_tx_status_m1;
end
end
// drp mux
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_es_drp_rdata <= 'd0;
up_es_drp_ready <= 'd0;
up_drp_rdata_int <= 'd0;
up_drp_ready_int <= 'd0;
end else begin
if (up_es_status == 1'b1) begin
up_drp_sel <= up_es_drp_sel;
up_drp_wr <= up_es_drp_wr;
up_drp_addr <= up_es_drp_addr;
up_drp_wdata <= up_es_drp_wdata;
up_es_drp_rdata <= up_drp_rdata;
up_es_drp_ready <= up_drp_ready;
up_drp_rdata_int <= 16'd0;
up_drp_ready_int <= 1'd0;
end else begin
up_drp_sel <= up_drp_sel_int;
up_drp_wr <= up_drp_wr_int;
up_drp_addr <= up_drp_addr_int;
up_drp_wdata <= up_drp_wdata_int;
up_es_drp_rdata <= 16'd0;
up_es_drp_ready <= 1'd0;
up_drp_rdata_int <= up_drp_rdata;
up_drp_ready_int <= up_drp_ready;
end
end
end
// rx sysref & sync
always @(posedge rx_clk) begin
if (rx_rst_m == 1'b1) begin
rx_sysref_sel_m1 <= 'd0;
rx_sysref_sel <= 'd0;
rx_up_sysref_m1 <= 'd0;
rx_up_sysref <= 'd0;
rx_ip_sysref <= 'd0;
rx_up_sync_m1 <= 'd0;
rx_up_sync <= 'd0;
rx_sync <= 'd0;
end else begin
rx_sysref_sel_m1 <= up_rx_sysref_sel;
rx_sysref_sel <= rx_sysref_sel_m1;
rx_up_sysref_m1 <= up_rx_sysref;
rx_up_sysref <= rx_up_sysref_m1;
if (rx_sysref_sel_m1 == 1'b1) begin
rx_ip_sysref <= rx_sysref;
end else begin
rx_ip_sysref <= rx_up_sysref;
end
rx_up_sync_m1 <= up_rx_sync;
rx_up_sync <= rx_up_sync_m1;
rx_sync <= rx_up_sync & rx_ip_sync;
end
end
// tx sysref & sync
always @(posedge tx_clk) begin
if (tx_rst_m == 1'b1) begin
tx_sysref_sel_m1 <= 'd0;
tx_sysref_sel <= 'd0;
tx_up_sysref_m1 <= 'd0;
tx_up_sysref <= 'd0;
tx_ip_sysref <= 'd0;
tx_up_sync_m1 <= 'd0;
tx_up_sync <= 'd0;
tx_ip_sync <= 'd0;
end else begin
tx_sysref_sel_m1 <= up_tx_sysref_sel;
tx_sysref_sel <= tx_sysref_sel_m1;
tx_up_sysref_m1 <= up_tx_sysref;
tx_up_sysref <= tx_up_sysref_m1;
if (tx_sysref_sel_m1 == 1'b1) begin
tx_ip_sysref <= tx_sysref;
end else begin
tx_ip_sysref <= tx_up_sysref;
end
tx_up_sync_m1 <= up_tx_sync;
tx_up_sync <= tx_up_sync_m1;
tx_ip_sync <= tx_up_sync & tx_sync;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************