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adrv9379:ZCU102: Initial commit

main
Adrian Costina 2018-04-10 15:06:32 +03:00
parent f3102eea5a
commit e4c4559b6d
5 changed files with 416 additions and 0 deletions
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projects/adrv9379/zcu102/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := adrv9379_zcu102
M_DEPS += ../common/adrv9379_bd.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_ad9379
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_cpack
LIB_DEPS += util_dacfifo
LIB_DEPS += util_upack
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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projects/adrv9379/zcu102/system_bd.tcl Normal file
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set dac_fifo_name axi_ad9379_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
source ../common/adrv9379_bd.tcl
ad_connect sys_dma_clk sys_ps8/pl_clk2
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter util_ad9379_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter util_ad9379_xcvr CONFIG.QPLL_FBDIV 80
ad_ip_parameter util_ad9379_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.DEVICE_TYPE 2
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.DEVICE_TYPE 2

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projects/adrv9379/zcu102/system_constr.xdc Normal file
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# ad9379
set_property -dict {PACKAGE_PIN G8 } [get_ports ref_clk0_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P (NC)
set_property -dict {PACKAGE_PIN G7 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N (NC)
set_property -dict {PACKAGE_PIN L8 } [get_ports ref_clk1_p] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_P
set_property -dict {PACKAGE_PIN L7 } [get_ports ref_clk1_n] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_N
set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[0]] ; ## A02 FMC_HPC0_DP1_M2C_P
set_property -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[0]] ; ## A03 FMC_HPC0_DP1_M2C_N
set_property -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[1]] ; ## A06 FMC_HPC0_DP2_M2C_P
set_property -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[1]] ; ## A07 FMC_HPC0_DP2_M2C_N
set_property -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[2]] ; ## C06 FMC_HPC0_DP0_M2C_P
set_property -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[2]] ; ## C07 FMC_HPC0_DP0_M2C_N
set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC0_DP3_M2C_P
set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC0_DP3_M2C_N
set_property -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC0_DP1_C2M_P (tx_data_p[0])
set_property -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC0_DP1_C2M_N (tx_data_n[0])
set_property -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC0_DP2_C2M_P (tx_data_p[3])
set_property -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC0_DP2_C2M_N (tx_data_n[3])
set_property -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[2]] ; ## C02 FMC_HPC0_DP0_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC0_DP0_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC0_DP3_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC0_DP3_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## G09 FMC_HPC0_LA03_P
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## G10 FMC_HPC0_LA03_N
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVDS} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC0_LA25_P (Sniffer)
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVDS} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC0_LA25_N (Sniffer)
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## H07 FMC_HPC0_LA02_P
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## H08 FMC_HPC0_LA02_N
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_p] ; ## G06 FMC_HPC0_LA00_CC_P
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_n] ; ## G07 FMC_HPC0_LA00_CC_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_p] ; ## H28 FMC_HPC0_LA24_P
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_n] ; ## H29 FMC_HPC0_LA24_N
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS } [get_ports sysref_out_p] ; ## D08 FMC_HPC0_LA09_P
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS } [get_ports sysref_out_n] ; ## D09 FMC_HPC0_LA09_N
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC0_LA01_CC_N
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9379] ; ## D14 FMC_HPC0_LA01_CC_P
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H13 FMC_HPC0_LA07_P
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H14 FMC_HPC0_LA07_N
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G12 FMC_HPC0_LA08_P
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC0_LA18_CC_P
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC0_LA18_CC_N
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports ad9379_tx1_enable] ; ## D17 FMC_HPC0_LA13_P
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports ad9379_tx2_enable] ; ## C18 FMC_HPC0_LA14_P
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports ad9379_rx1_enable] ; ## D18 FMC_HPC0_LA13_N
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports ad9379_rx2_enable] ; ## C19 FMC_HPC0_LA14_N
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports ad9379_test] ; ## D11 FMC_HPC0_LA05_P
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18} [get_ports ad9379_reset_b] ; ## H10 FMC_HPC0_LA04_P
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18} [get_ports ad9379_gpint] ; ## H11 FMC_HPC0_LA04_N
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_00] ; ## H19 FMC_HPC0_LA15_P
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_01] ; ## H20 FMC_HPC0_LA15_N
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_02] ; ## G18 FMC_HPC0_LA16_P
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_03] ; ## G19 FMC_HPC0_LA16_N
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_04] ; ## H25 FMC_HPC0_LA21_P
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_05] ; ## H26 FMC_HPC0_LA21_N
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_06] ; ## C22 FMC_HPC0_LA26_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_07] ; ## C23 FMC_HPC0_LA26_N
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_08] ; ## G25 FMC_HPC0_LA22_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_09] ; ## H22 FMC_HPC0_LA19_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_10] ; ## H23 FMC_HPC0_LA19_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_11] ; ## G21 FMC_HPC0_LA20_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_12] ; ## G22 FMC_HPC0_LA20_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_13] ; ## G31 FMC_HPC0_LA29_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_14] ; ## G30 FMC_HPC0_LA29_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_15] ; ## G24 FMC_HPC0_LA22_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_16] ; ## G03 FMC_HPC0_CLK1_M2C_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_17] ; ## G02 FMC_HPC0_CLK1_M2C_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports ad9379_gpio_18] ; ## D12 FMC_HPC0_LA05_N
# clocks
create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p]
create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx adrv9379_zcu102
adi_project_files adrv9379_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run adrv9379_zcu102

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
inout iic_scl,
inout iic_sda,
input ref_clk0_p,
input ref_clk0_n,
input ref_clk1_p,
input ref_clk1_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output [ 3:0] tx_data_p,
output [ 3:0] tx_data_n,
output rx_sync_p,
output rx_sync_n,
output rx_os_sync_p,
output rx_os_sync_n,
input tx_sync_p,
input tx_sync_n,
input tx_sync_1_p,
input tx_sync_1_n,
input sysref_p,
input sysref_n,
output sysref_out_p,
output sysref_out_n,
output spi_csn_ad9528,
output spi_csn_ad9379,
output spi_clk,
output spi_mosi,
input spi_miso,
inout ad9528_reset_b,
inout ad9528_sysref_req,
inout ad9379_tx1_enable,
inout ad9379_tx2_enable,
inout ad9379_rx1_enable,
inout ad9379_rx2_enable,
inout ad9379_test,
inout ad9379_reset_b,
inout ad9379_gpint,
inout ad9379_gpio_00,
inout ad9379_gpio_01,
inout ad9379_gpio_02,
inout ad9379_gpio_03,
inout ad9379_gpio_04,
inout ad9379_gpio_05,
inout ad9379_gpio_06,
inout ad9379_gpio_07,
inout ad9379_gpio_15,
inout ad9379_gpio_08,
inout ad9379_gpio_09,
inout ad9379_gpio_10,
inout ad9379_gpio_11,
inout ad9379_gpio_12,
inout ad9379_gpio_14,
inout ad9379_gpio_13,
inout ad9379_gpio_17,
inout ad9379_gpio_16,
inout ad9379_gpio_18);
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire [20:0] gpio_bd;
wire [ 2:0] spi_csn;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire rx_os_sync;
wire tx_sync;
wire sysref;
assign gpio_i[94:60] = gpio_o[94:60];
assign gpio_i[31:21] = gpio_o[31:21];
assign sysref_out = 0;
// instantiations
IBUFDS_GTE4 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE4 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_rx_os_sync (
.I (rx_os_sync),
.O (rx_os_sync_p),
.OB (rx_os_sync_n));
OBUFDS i_obufds_sysref_out (
.I (sysref_out),
.O (sysref_out_p),
.OB (sysref_out_n));
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_1_p),
.IB (tx_sync_1_n),
.O (tx_sync_1));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
.dio_p ({ ad9528_reset_b, // 59
ad9528_sysref_req, // 58
ad9379_tx1_enable, // 57
ad9379_tx2_enable, // 56
ad9379_rx1_enable, // 55
ad9379_rx2_enable, // 54
ad9379_test, // 53
ad9379_reset_b, // 52
ad9379_gpint, // 51
ad9379_gpio_00, // 50
ad9379_gpio_01, // 49
ad9379_gpio_02, // 48
ad9379_gpio_03, // 47
ad9379_gpio_04, // 46
ad9379_gpio_05, // 45
ad9379_gpio_06, // 44
ad9379_gpio_07, // 43
ad9379_gpio_15, // 42
ad9379_gpio_08, // 41
ad9379_gpio_09, // 40
ad9379_gpio_10, // 39
ad9379_gpio_11, // 38
ad9379_gpio_12, // 37
ad9379_gpio_14, // 36
ad9379_gpio_13, // 35
ad9379_gpio_17, // 34
ad9379_gpio_16, // 33
ad9379_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
assign gpio_bd_i = gpio_bd[20:8];
assign gpio_bd_o = gpio_bd[ 7:0];
assign spi_csn_ad9528 = spi_csn[0];
assign spi_csn_ad9379 = spi_csn[1];
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.ps_intr_00 (1'd0),
.ps_intr_01 (1'd0),
.ps_intr_02 (1'd0),
.ps_intr_03 (1'd0),
.ps_intr_04 (1'd0),
.ps_intr_05 (1'd0),
.ps_intr_06 (1'd0),
.ps_intr_07 (1'd0),
.ps_intr_14 (1'd0),
.ps_intr_15 (1'd0),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk1),
.rx_ref_clk_2 (ref_clk1),
.rx_sync_0 (rx_sync),
.rx_sync_2 (rx_os_sync),
.rx_sysref_0 (sysref),
.rx_sysref_2 (sysref),
.spi0_sclk (spi_clk),
.spi0_csn (spi_csn),
.spi0_miso (spi_miso),
.spi0_mosi (spi_mosi),
.spi1_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi (),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_ref_clk_0 (ref_clk1),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref));
endmodule
// ***************************************************************************
// ***************************************************************************